The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core:
Rotation,Translation, Sin and Cos, Arctan. Two architecture configurations are available
for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial,
with multiple cycles throughput. The input data, output data widths and iterative number
are configurable over a wide range. The IP core uses full internal precision while allowing
variable output precision with several choices for rounding.
Crosslink-NX (LIFCL-40, LIFCL-17), Certus-NX (LFD2NX-40, LFD2NX-17, LFD2NX-9, LFD2NX-28), CertusPro-NX (LFCPNX-50, LFCPNX-100), MachXO5-NX (LFMXO5-25, LFMXO5-55T, LFMXO5-100T), Certus-NX-RT (UT24C40), CertusPro-NX-RT(UT24CP100), Avant(LAV-AT-E70, LAV-AT-G70, LAV-AT-X70), Certus-KH(LN2-CT-20)
| 1.5.0 |
Added Propel Support. Added Certus-N2 Support. |
| 1.4.0 | Updated IP constraint |
| 1.3.0 | Added LAV-AT, UT24C and UT24CP support. |
| 1.2.0 | Added LFMXO5 support. |
| 1.1.0 | Added LFCPNX support. |
| 1.0.0 | Intial release. |