The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core:
Rotation,Translation, Sin and Cos, Arctan. Two architecture configurations are available
for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial,
with multiple cycles throughput. The input data, output data widths and iterative number
are configurable over a wide range. The IP core uses full internal precision while allowing
variable output precision with several choices for rounding.
LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100, LFMXO5-25
| 1.2.0 | Added LFMXO5 support. |
| 1.1.0 | Added LFCPNX support. |
| 1.0.0 | Intial release. |