<?xml version="1.0" ?>
<lsccip:ip xmlns:lsccip="http://www.latticesemi.com/XMLSchema/Radiant/ip" xmlns:xi="http://www.w3.org/2001/XInclude" version="1.0">
    <lsccip:general>
        <lsccip:vendor>latticesemi.com</lsccip:vendor>
        <lsccip:library>ip</lsccip:library>
        <lsccip:name>axi_register_slice</lsccip:name>
        <lsccip:display_name>AXI Register Slice</lsccip:display_name>
        <lsccip:version>1.3.0</lsccip:version>
        <lsccip:category>Processors_Controllers_and_Peripherals</lsccip:category>
        <lsccip:min_radiant_version>3.2</lsccip:min_radiant_version>
        <lsccip:min_esi_version>2023.1</lsccip:min_esi_version>
        <lsccip:supported_products>
            <lsccip:supported_family name="LIFCL"/>
            <lsccip:supported_family name="LFD2NX"/>
            <lsccip:supported_family name="LFMXO5"/>
            <lsccip:supported_family name="LFCPNX"/>
            <lsccip:supported_family name="LAV-AT"/>
            <lsccip:supported_family name="LN2-CT"/>
            <lsccip:supported_family name="LN2-MH"/>
            <lsccip:supported_family name="ECP5U"/>
            <lsccip:supported_family name="ECP5UM"/>
            <lsccip:supported_family name="ECP5UM5G"/>
            <lsccip:supported_family name="LatticeECP3"/>
        </lsccip:supported_products>
        <lsccip:supported_platforms>
          <lsccip:supported_platform name="radiant"/>
          <lsccip:supported_platform name="esi"/>
        </lsccip:supported_platforms>
    </lsccip:general>
    <lsccip:settings>
        <lsccip:setting conn_mod="axi_register_slice_top" id="axi_protocol" type="input" value_type="string" title="AXI Protocol" default="AXI4" options="['AXI4', 'AXI3', 'AXI4LITE']" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_PROTOCOL" type="param" value_type="int" title="AXI Protocol" default="0" editable="False" hidden="True" value_expr="0 if (axi_protocol == 'AXI4') else (1 if (axi_protocol == 'AXI3') else 2)" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="axi_supports_user_signals" type="input" value_type="bool" title="User Signals Enable/Disable" default="False" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_SUPPORTS_USER_SIGNALS" type="param" value_type="int" title="User Signals Enable/Disable" default="0" editable="False" hidden="True" value_expr="1 if (axi_supports_user_signals == True) else 0" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_ID_WIDTH" type="param" value_type="int" title="Address Id Width" default="4" value_range="(1,32)" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_ADDR_WIDTH" type="param" value_type="int" title="Address Width" default="32" value_range="(1,64) if (axi_protocol == 'AXI4LITE') else (12,64)" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_DATA_WIDTH" type="param" value_type="int" title="Data Width" default="32" options="[32 , 64] if (axi_protocol == 'AXI4LITE') else [32 , 64 , 128, 256, 512, 1024]" config_groups="'SystemBuilder'" group1="General"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_AWUSER_WIDTH" type="param" value_type="int" title="Write Address User Width" default="1" value_range="(1,1024)" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_ARUSER_WIDTH" type="param" value_type="int" title="Read Address User Width" default="1" value_range="(1,1024)" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_WUSER_WIDTH" type="param" value_type="int" title="Write Data User Width" default="1" value_range="(1,1024)" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_RUSER_WIDTH" type="param" value_type="int" title="Read Data User Width" default="1" value_range="(1,1024)" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="AXI_BUSER_WIDTH" type="param" value_type="int" title="Write Response User Width" default="1" value_range="(1,1024)" hidden="False if(AXI_PROTOCOL==0) else True" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="reg_config_aw" type="input" value_type="string" title="Register Configuration Mode For Write Address Channel" default="Full" options="['Full', 'Light', 'Inputs']" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="REG_CONFIG_AW" type="param" value_type="int" title="Register Configuration Mode For Write Address Channel" default="0" editable="False" hidden="True" value_expr="0 if (reg_config_aw == 'Full') else (1 if (reg_config_aw == 'Light') else 2)" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="reg_config_w" type="input" value_type="string" title="Register Configuration Mode For Write Data Channel" default="Full" options="['Full', 'Light', 'Inputs']" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="REG_CONFIG_W" type="param" value_type="int" title="Register Configuration Mode For Address Write Data Channel" default="0" editable="False" hidden="True" value_expr="0 if (reg_config_w == 'Full') else (1 if (reg_config_w == 'Light') else 2)" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="reg_config_b" type="input" value_type="string" title="Register Configuration Mode For Write Response Channel" default="Full" options="['Full', 'Light', 'Inputs']" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="REG_CONFIG_B" type="param" value_type="int" title="Register Configuration Mode For Write Response Channel" default="0" editable="False" hidden="True" value_expr="0 if (reg_config_b == 'Full') else (1 if (reg_config_b == 'Light') else 2)" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="reg_config_ar" type="input" value_type="string" title="Register Configuration Mode For Read Address Channel" default="Full" options="['Full', 'Light', 'Inputs']" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="REG_CONFIG_AR" type="param" value_type="int" title="Register Configuration Mode For Read Address Channel" default="0" editable="False" hidden="True" value_expr="0 if (reg_config_ar == 'Full') else (1 if (reg_config_ar == 'Light') else 2)" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="reg_config_r" type="input" value_type="string" title="Register Configuration Mode For Read Data Channel" default="Full" options="['Full', 'Light', 'Inputs']" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
        <lsccip:setting conn_mod="axi_register_slice_top" id="REG_CONFIG_R" type="param" value_type="int" title="Register Configuration Mode For Read Data Channel" default="0" editable="False" hidden="True" value_expr="0 if (reg_config_r == 'Full') else (1 if (reg_config_r == 'Light') else 2)" config_groups="'SystemBuilder'" group1="Capabilities and Configuration Read-Only Values"/>
    </lsccip:settings>
    <lsccip:ports>
        <lsccip:port name="a_clk_i" dir="in" conn_mod="axi_register_slice_top" conn_port="a_clk_i" port_type="clock"/>
        <lsccip:port name="a_reset_n_i" dir="in" conn_mod="axi_register_slice_top" conn_port="a_reset_n_i" port_type="reset"/>
        <lsccip:port name="s_axi_awid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awid_i" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awaddr_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awaddr_i" range="((AXI_ADDR_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awlen_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awlen_i" range="((4 if AXI_PROTOCOL == 1 else 8)-1, 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awsize_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awsize_i" range="((3-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awburst_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awburst_i" range="((2-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awlock_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awlock_i" range="(((2 if AXI_PROTOCOL == 1 else 1)-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awcache_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awcache_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awprot_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awprot_i" range="((3-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awregion_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awregion_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awqos_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awqos_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awuser_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awuser_i" range="((AXI_AWUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awvalid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_awvalid_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_awready_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_awready_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wdata_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_wdata_i" range="((AXI_DATA_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wstrb_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_wstrb_i" range="(int((AXI_DATA_WIDTH/8)-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wlast_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_wlast_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wuser_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_wuser_i" range="((AXI_WUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wvalid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_wvalid_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_wready_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_wready_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_bid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_bid_o" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_bresp_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_bresp_o" range="((2-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_buser_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_buser_o" range="((AXI_BUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_bvalid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_bvalid_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_bready_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_bready_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arid_i" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_araddr_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_araddr_i" range="((AXI_ADDR_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arlen_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arlen_i" range="((((4 if AXI_PROTOCOL == 1 else 8))-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arsize_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arsize_i" range="((3-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arburst_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arburst_i" range="((2-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arlock_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arlock_i" range="(((2 if AXI_PROTOCOL == 1 else 1)-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arcache_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arcache_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arprot_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arprot_i" range="((3-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arregion_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arregion_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arqos_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arqos_i" range="((4-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_aruser_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_aruser_i" range="((AXI_ARUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arvalid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_arvalid_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_arready_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_arready_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_rid_o" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rdata_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_rdata_o" range="((AXI_DATA_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rresp_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_rresp_o" range="((2-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rlast_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_rlast_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_ruser_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_ruser_o" range="((AXI_RUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rvalid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="s_axi_rvalid_o" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="s_axi_rready_i" dir="in" conn_mod="axi_register_slice_top" conn_port="s_axi_rready_i" bus_interface=" 'AXI4_S' if AXI_PROTOCOL ==0 else 'AXI4L_S'"/>
        <lsccip:port name="m_axi_awid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awid_o" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awaddr_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awaddr_o" range="((AXI_ADDR_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awlen_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awlen_o" range="(((4 if AXI_PROTOCOL == 1 else 8)-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awsize_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awsize_o" range="((3-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awburst_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awburst_o" range="((2-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awlock_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awlock_o" range="(((2 if AXI_PROTOCOL == 1 else 1)-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awcache_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awcache_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awprot_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awprot_o" range="((3-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awregion_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awregion_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awqos_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awqos_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awuser_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awuser_o" range="((AXI_AWUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awvalid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_awvalid_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_awready_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_awready_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wdata_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_wdata_o" range="((AXI_DATA_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wstrb_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_wstrb_o" range="(int(AXI_DATA_WIDTH/8-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wlast_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_wlast_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wuser_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_wuser_o" range="((AXI_WUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wvalid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_wvalid_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_wready_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_wready_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_bid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_bid_i" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_bresp_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_bresp_i" range="((2-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_buser_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_buser_i" range="((AXI_BUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_bvalid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_bvalid_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_bready_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_bready_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arid_o" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_araddr_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_araddr_o" range="((AXI_ADDR_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arlen_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arlen_o" range="(((4 if AXI_PROTOCOL == 1 else 8)-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arsize_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arsize_o" range="((3-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arburst_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arburst_o" range="((2-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arlock_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arlock_o" range="(((2 if AXI_PROTOCOL == 1 else 1)-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arcache_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arcache_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arprot_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arprot_o" range="((3-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arregion_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arregion_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arqos_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arqos_o" range="((4-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_aruser_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_aruser_o" range="((AXI_ARUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arvalid_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_arvalid_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_arready_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_arready_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_rid_i" range="((AXI_ID_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rdata_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_rdata_i" range="((AXI_DATA_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rresp_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_rresp_i" range="((2-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rlast_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_rlast_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_ruser_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_ruser_i" range="((AXI_RUSER_WIDTH-1), 0)" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rvalid_i" dir="in" conn_mod="axi_register_slice_top" conn_port="m_axi_rvalid_i" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
        <lsccip:port name="m_axi_rready_o" dir="out" conn_mod="axi_register_slice_top" conn_port="m_axi_rready_o" bus_interface=" 'AXI4_M' if AXI_PROTOCOL ==0 else 'AXI4L_M'"/>
    </lsccip:ports>
    <xi:include parse="xml" href="bus_interface.xml"/>
    <lsccip:parameters>
        <lsccip:parameter>
            <lsccip:name>SB_COMPONENT_TYPE</lsccip:name>
            <lsccip:value>Bus</lsccip:value>
        </lsccip:parameter>
    </lsccip:parameters>
</lsccip:ip>
