AXI4 Interconnect

Description

The AMBA AXI is for high-performance, high clock frequency system modules. The AXI acts as the high-performance system backbone bus. AXI supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macrocell functions.

Devices Supported

LIFCL, LFD2NX, LFMXO5, LFCPNX, LAV-AT

References

Revision History

2.0.1 This is an update to extend device supportability and to address several issues:
1. Sending a series of "Write Address" transactions and hit max outstanding transactions, resulting in incorrect behavior (e.g. missing transactions).
2. When having a combination of data width up conversion and data width down conversion and the "AXI Manager Max Data Width" being a different value than "AXI Subordinate Max Data Width", there may be incorrect behavior.
3. Out of Order read responses not handled correctly with data width up conversion.
4. WVALID to external subordinate has an unintended dependency on AWREADY, causing transaction to hang when AWREADY assertion depends on both AWVALID and WVALID assertion.
2.0.0 This is a major upgrade. Changes involved extending support to all Nexus devices as well as changing the width conversion implementation to improve throughput, maximum supported frequency and resource utilization. Refer to User Guide for more details.
1.2.2 Removed axi_s_aclken_i and axi_m_aclken_i ports. Clock gating logic has been removed.
1.2.1 Increased the maximum fragmented address space from 8 to 16 fragments per external subordinate
1.2.0 Changed the default value of AXI User Width, AXI Manager Max no. of ID supports, External Manager No. of IDs , External Manager Write accept, External Manager Read accept, External Subordinate Write Issue , and External Subordinate Read Issue in User Guide Table 2.2. Attributes Table
1.1.0 Added LAV-AT support
1.0.0 Initial release