<?xml version="1.0" ?>
<lsccip:ip xmlns:lsccip="http://www.latticesemi.com/XMLSchema/Radiant/ip" xmlns:xi="http://www.w3.org/2001/XInclude" version="1.0">
    <lsccip:general>
        <lsccip:vendor>latticesemi.com</lsccip:vendor>
        <lsccip:library>ip</lsccip:library>
        <lsccip:name>axi2ahb_bridge</lsccip:name>
        <lsccip:display_name>AXI4 to AHB-Lite Bridge</lsccip:display_name>
        <lsccip:version>1.6.0</lsccip:version>
        <lsccip:category>Processors_Controllers_and_Peripherals</lsccip:category>
        <lsccip:min_radiant_version>3.2</lsccip:min_radiant_version>
        <lsccip:min_esi_version>2022.1</lsccip:min_esi_version>
        <lsccip:supported_products>
            <lsccip:supported_family name="LIFCL"/>
            <lsccip:supported_family name="LFD2NX"/>
            <lsccip:supported_family name="LFMXO5"/>
            <lsccip:supported_family name="LFCPNX"/>
            <lsccip:supported_family name="LAV-AT"/>
            <lsccip:supported_family name="LN2-CT"/>
            <lsccip:supported_family name="LN2-MH"/>
            <lsccip:supported_family name="ECP5U"/>
            <lsccip:supported_family name="ECP5UM"/>
            <lsccip:supported_family name="ECP5UM5G"/>
            <lsccip:supported_family name="LatticeECP3"/>
        </lsccip:supported_products>
        <lsccip:supported_platforms>
          <lsccip:supported_platform name="esi"/>
          <lsccip:supported_platform name="radiant"/>
        </lsccip:supported_platforms>
    </lsccip:general>
    <lsccip:settings>
        <lsccip:setting conn_mod="lscc_axi2ahb_lite" group1="General" id="AXI_AHB_DATA_WIDTH" type="param" value_type="int" default="32" options="[8,16,32,64,128,256,512,1024] if AXI4_LITE==False else [32,64]" title="AXI_AHB Data bus width"/>
        <lsccip:setting conn_mod="lscc_axi2ahb_lite" group1="General" id="AXI_ID_WIDTH" type="param" value_type="int" default="8" options="range(1,12)" title="AXI ID width"/>
        <lsccip:setting conn_mod="lscc_axi2ahb_lite" group1="General" id="AXI_USER_WIDTH" type="param" value_type="int" default="4" options="range(1,129)" title="AXI User Width"/>
        <lsccip:setting conn_mod="lscc_axi2ahb_lite" group1="General" id="AXI4_LITE" type="param" value_type="bool" default="False" editable="True" title="AXI4 Lite"/>
    </lsccip:settings>
    <lsccip:ports>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="aclk_i" name="aclk_i" dir="in" port_type="clock"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="aresetn_i" name="aresetn_i" dir="in" port_type="reset"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_sel_o" name="ahb_mas_sel_o" dir="out" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_addr_o" name="ahb_mas_addr_o" dir="out" range="(31,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_write_o" name="ahb_mas_write_o" dir="out" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_wdata_o" name="ahb_mas_wdata_o" dir="out" range="(AXI_AHB_DATA_WIDTH-1,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_size_o" name="ahb_mas_size_o" dir="out" range="(2,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_trans_o" name="ahb_mas_trans_o" dir="out" range="(1,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_burst_o" name="ahb_mas_burst_o" dir="out" range="(2,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_prot_o" name="ahb_mas_prot_o" dir="out" range="(3,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_ready_o" name="ahb_mas_ready_o" dir="out" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_ready_i" name="ahb_mas_ready_i" dir="in" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_rdata_i" name="ahb_mas_rdata_i" dir="in" range="(AXI_AHB_DATA_WIDTH-1,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_resp_i" name="ahb_mas_resp_i" dir="in" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="ahb_mas_mastlock_o" name="ahb_mas_mastlock_o" dir="out" range="(0,0)" bus_interface="AHBL_M"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awvalid_i" name="axi_slv_awvalid_i" dir="in" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awready_o" name="axi_slv_awready_o" dir="out" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awaddr_i" name="axi_slv_awaddr_i" dir="in" range="(31,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awsize_i" name="axi_slv_awsize_i" dir="in" stick_low="AXI4_LITE==True" range="(2,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awburst_i" name="axi_slv_awburst_i" dir="in" stick_low="AXI4_LITE==True" range="(1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awlock_i" name="axi_slv_awlock_i" dir="in" stick_low="AXI4_LITE==True" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awlen_i" name="axi_slv_awlen_i" dir="in" stick_low="AXI4_LITE==True" range="(7,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awid_i" name="axi_slv_awid_i" dir="in" stick_low="AXI4_LITE==True" range="(AXI_ID_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awprot_i" name="axi_slv_awprot_i" dir="in" range="(2,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awcache_i" name="axi_slv_awcache_i" dir="in" stick_low="AXI4_LITE==True" range="(3,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awqos_i" name="axi_slv_awqos_i" dir="in" range="(3,0)" stick_low="AXI4_LITE==True" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awregion_i" name="axi_slv_awregion_i" dir="in" stick_low="AXI4_LITE==True" range="(3,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_awuser_i" name="axi_slv_awuser_i" dir="in" stick_low="AXI4_LITE==True" range="(AXI_USER_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wvalid_i" name="axi_slv_wvalid_i" dir="in" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wdata_i" name="axi_slv_wdata_i" dir="in" range="(AXI_AHB_DATA_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wlast_i" name="axi_slv_wlast_i" dir="in" stick_low="AXI4_LITE==True" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wuser_i" name="axi_slv_wuser_i" dir="in" stick_low="AXI4_LITE==True" range="(AXI_USER_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wstrb_i" name="axi_slv_wstrb_i" dir="in" range="(int(AXI_AHB_DATA_WIDTH/8)-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_wready_o" name="axi_slv_wready_o" dir="out" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_bvalid_o" name="axi_slv_bvalid_o" dir="out" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_bready_i" name="axi_slv_bready_i" dir="in" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_bresp_o" name="axi_slv_bresp_o" dir="out" range="(1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_buser_o" name="axi_slv_buser_o" dir="out" dangling="AXI4_LITE==True" range="(AXI_USER_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_bid_o" name="axi_slv_bid_o" dir="out" dangling="AXI4_LITE==True" range="(AXI_ID_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arvalid_i" name="axi_slv_arvalid_i" dir="in" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arready_o" name="axi_slv_arready_o" dir="out" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_araddr_i" name="axi_slv_araddr_i" dir="in" range="(31,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arsize_i" name="axi_slv_arsize_i" dir="in" stick_low="AXI4_LITE==True" range="(2,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arburst_i" name="axi_slv_arburst_i" dir="in" stick_low="AXI4_LITE==True" range="(1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arlock_i" name="axi_slv_arlock_i" dir="in" stick_low="AXI4_LITE==True" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arlen_i" name="axi_slv_arlen_i" dir="in" stick_low="AXI4_LITE==True" range="(7,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arid_i" name="axi_slv_arid_i" dir="in" stick_low="AXI4_LITE==True" range="(AXI_ID_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arprot_i" name="axi_slv_arprot_i" dir="in" range="(2,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arcache_i" name="axi_slv_arcache_i" dir="in" stick_low="AXI4_LITE==True" range="(3,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arqos_i" name="axi_slv_arqos_i" dir="in" stick_low="AXI4_LITE==True" range="(3,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_arregion_i" name="axi_slv_arregion_i" dir="in" stick_low="AXI4_LITE==True" range="(3,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_aruser_i" name="axi_slv_aruser_i" dir="in" stick_low="AXI4_LITE==True" range="(AXI_USER_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rvalid_o" name="axi_slv_rvalid_o" dir="out" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rready_i" name="axi_slv_rready_i" dir="in" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rdata_o" name="axi_slv_rdata_o" dir="out" range="(AXI_AHB_DATA_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rlast_o" name="axi_slv_rlast_o" dir="out" dangling="AXI4_LITE==True" range="(0,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rresp_o" name="axi_slv_rresp_o" dir="out" range="(1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_ruser_o" name="axi_slv_ruser_o" dir="out" dangling="AXI4_LITE==True" range="(AXI_USER_WIDTH-1,0)" bus_interface="AXI4_S"/>
        <lsccip:port conn_mod="lscc_axi2ahb_lite" conn_port="axi_slv_rid_o" name="axi_slv_rid_o" dir="out" dangling="AXI4_LITE==True" range="(AXI_ID_WIDTH-1,0)" bus_interface="AXI4_S"/>
    </lsccip:ports>
    <xi:include href="bus_interface.xml" parse="xml"/>
    <lsccip:parameters>
        <lsccip:parameter>
            <lsccip:name>SB_COMPONENT_TYPE</lsccip:name>
            <lsccip:value>Bridge</lsccip:value>
        </lsccip:parameter>
    </lsccip:parameters>
</lsccip:ip>
