<?xml version="1.0" ?>
<lsccip:ip xmlns:lsccip="http://www.latticesemi.com/XMLSchema/Radiant/ip" xmlns:xi="http://www.w3.org/2001/XInclude" version="1.0">
    <lsccip:general>
        <lsccip:vendor>latticesemi.com</lsccip:vendor>
        <lsccip:library>ip</lsccip:library>
        <lsccip:name>ahbl2axi4</lsccip:name>
        <lsccip:display_name>AHB-Lite to AXI4 Bridge</lsccip:display_name>
        <lsccip:version>1.5.0</lsccip:version>
        <lsccip:category>Processors_Controllers_and_Peripherals</lsccip:category>
        <lsccip:min_radiant_version>2023.1</lsccip:min_radiant_version>
        <lsccip:min_esi_version>2023.1</lsccip:min_esi_version>
        <lsccip:supported_products>
            <lsccip:supported_family name="LIFCL"/>
            <lsccip:supported_family name="LFD2NX"/>
            <lsccip:supported_family name="LFMXO5"/>
            <lsccip:supported_family name="LFCPNX"/>
            <lsccip:supported_family name="LAV-AT"/>
            <lsccip:supported_family name="LN2-CT"/>
            <lsccip:supported_family name="LN2-MH"/>
            <lsccip:supported_family name="ECP5U"/>
            <lsccip:supported_family name="ECP5UM"/>
            <lsccip:supported_family name="ECP5UM5G"/>
            <lsccip:supported_family name="LatticeECP3"/>
        </lsccip:supported_products>
        <lsccip:supported_platforms>
          <lsccip:supported_platform name="esi"/>
          <lsccip:supported_platform name="radiant"/>
        </lsccip:supported_platforms>
    </lsccip:general>
    <lsccip:settings>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="M_ADDR_WIDTH" title="Address Width(bits)" type="param" value_type="int" default="32" options="range(11,33)" editable="True" hidden="False" config_groups="'SystemBuilder'" description="Address width of both AHB Lite and AXI4 interfaces" group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="DATA_WIDTH" title="Data Bus Width(bits)" type="param" value_type="int" default="32" options="[8,16,32,64,128,256,512,1024] if AXI4_LITE==False else [32,64]" editable="True" hidden="False" config_groups="'SystemBuilder'" description="Data width of both AHB Lite and AXI4 interfaces." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="AXI_ID_WIDTH" title="AXI ID Width(bits)" type="param" value_type="int" default="4" options="range(1,12)" editable="True" hidden="False" config_groups="'SystemBuilder'" description="This parameter controls only the bus width of the AXI's identification tag ports for read and write transaction. The value of the ID is always set to 0." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="AXI_SECURE_ACCESS" title="AXI Secure Access" type="param" value_type="bool" default="False" editable="True" hidden="False" description="Enable this parameter to support Secure operating states at AXI interface. This will always set AwProt/ArProt[1] to 0." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="AXI_TIMEOUT" title="AXI Timeout Counter" type="param" value_type="int" default="0" options="[0,16,32,64,128]" editable="True" hidden="False" description="Enable a timeout counter on AXI interface. The value determines how many clock cycle this bridge waits for a valid response before asserting a timeout flag: axi_timeout_o signal. A value of 0 means no timeout counter is generated." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="RDDATA_PIPELINE" title="Read Data bus Pipeline Enable" type="param" value_type="bool" default="False" editable="True" hidden="False" description="Enable this parameter to add a pipeline stage to Read Data bus to relax timing critical path on this bus." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="WRDATA_PIPELINE" title="Write Data bus Pipeline Enable" type="param" value_type="bool" default="False" editable="True" hidden="False" description="Enable this parameter to add a pipeline stage to Write Data bus to relax timing critical path on this bus." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="NARROW_TRANSFER" title="Narrow transfers support" type="param" value_type="bool" default="False" editable="not(DATA_WIDTH==8)" hidden="False" description="Enable this parameter to allow read/write transfers that are narrower than data bus." group1="General"/>
        <lsccip:setting conn_mod="lscc_ahbl2axi4" id="AXI4_LITE" title="AXI4 Lite support" type="param" value_type="bool" default="False" editable="True" hidden="False" description="Enable this parameter to convert to AXI4 Lite interface." group1="General"/>
    </lsccip:settings>
    <lsccip:ports>
        <lsccip:port name="clk_i" dir="in" conn_mod="lscc_ahbl2axi4" port_type="clock"/>
        <lsccip:port name="resetn_i" dir="in" conn_mod="lscc_ahbl2axi4" port_type="reset"/>
        <lsccip:port name="ahb_s_hsel_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_haddr_i" dir="in" range="(M_ADDR_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hwrite_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hwdata_i" dir="in" range="(DATA_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hsize_i" dir="in" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_htrans_i" dir="in" range="(1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hprot_i" dir="in" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hmastlock_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hburst_i" dir="in" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hready_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hreadyout_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hrdata_o" dir="out" range="(DATA_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="ahb_s_hresp_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AHBL_S" port_type="data"/>
        <lsccip:port name="axi_m_awid_o" dir="out" range="(AXI_ID_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awaddr_o" dir="out" range="(M_ADDR_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_awlen_o" dir="out" range="(7,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awsize_o" dir="out" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awburst_o" dir="out" range="(1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awlock_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awcache_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awprot_o" dir="out" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_awqos_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awregion_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_awvalid_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_awready_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_wdata_o" dir="out" range="(DATA_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_wstrb_o" dir="out" range="(int(DATA_WIDTH/8)-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_wlast_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_wvalid_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_wready_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_bid_i" dir="in" range="(AXI_ID_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" stick_low="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_bresp_i" dir="in" range="(1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_bvalid_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_bready_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_arid_o" dir="out" range="(AXI_ID_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_araddr_o" dir="out" range="(M_ADDR_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_arlen_o" dir="out" range="(7,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arsize_o" dir="out" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arburst_o" dir="out" range="(1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arlock_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arcache_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arprot_o" dir="out" range="(2,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_arqos_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arregion_o" dir="out" range="(3,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" dangling="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_arvalid_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_arready_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_rid_i" dir="in" range="(AXI_ID_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" stick_low="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_rdata_i" dir="in" range="(DATA_WIDTH-1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_rresp_i" dir="in" range="(1,0)" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_rlast_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data" stick_low="AXI4_LITE==True"/>
        <lsccip:port name="axi_m_rvalid_i" dir="in" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_m_rready_o" dir="out" conn_mod="lscc_ahbl2axi4" bus_interface="AXI4_M" port_type="data"/>
        <lsccip:port name="axi_timeout_o" dir="out" conn_mod="lscc_ahbl2axi4" dangling="(AXI_TIMEOUT == 0)" port_type="data"/>
    </lsccip:ports>
    <lsccip:outFileConfigs>
        <lsccip:fileConfig name="wrapper" skip_uniquify="false" file_suffix="sv" file_description="top_level_system_verilog"/>
    </lsccip:outFileConfigs>
    <xi:include href="bus_interface.xml" parse="xml"/>
    <lsccip:parameters>
        <lsccip:parameter>
            <lsccip:name>SB_COMPONENT_TYPE</lsccip:name>
            <lsccip:value>Bridge</lsccip:value>
        </lsccip:parameter>
    </lsccip:parameters>
</lsccip:ip>
