Advanced CNN Accelerator IP
Description
Documentation for Advanced CNN Accelerator IP
IMPORTANT NOTE
- Due to SystemVerilog components in the IP, to synthesize this IP in a design, the System Verilog standard
needs to be enabled in (right click) Implementation -> Properties -> "Verilog Standard" property.
-
After generation of IP, directly add the <generated IP>/rtl/<generated IP>.v file to current implementation instead of the IPX,
to enable propagation of SV standard for this IP to the Synplify Pro compiler.
Devices Supported
LFCPNX-100, LAV-AT-500E
References
Revision History
| 1.0.0 | First release for SensAI 6.0. |