/*
 * ------------------------------------------------------------------
     Copyright (c) 2023 by Lattice Semiconductor Corporation

     ALL RIGHTS RESERVED

------------------------------------------------------------------

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------------------------------------------------------------------
 *
 */

#include "usb_reset_seq.h"
#include "ltcusb.h"

uint32_t g_suspend_mode_enable;
uint32_t g_external_clock_enable;

int usb_reset_seq(void)
{
	/*
	 * Table 1-57.
	 * Global USB2 PHY Configuration Register.
	 */
	GUSB2PHYCFG0_data *gusb2phycfg0 = gusb2phycfg0_setup();

	/*
	 * USB 2.0 Turnaround Time (USBTrdTim).
	 */
	gusb2phycfg0->USBTRDTIM = 0x9;
	/*
	 * LS Inter-Packet Time (LSIPD).
	 */
	gusb2phycfg0->LSIPD = LSIPD_3_bit_times;

	/*
	 * UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal
	 * to be asserted to reset a UTMI PHY.
	 */
	gusb2phycfg0->PHYSOFTRST = 0x1;

	if(gusb2phycfg0_write() != 0)
	{
		return -1;
	}

	/*
	 * Table 1-61
	 * Global USB 3.0 PIPE Control Register
	 * The application uses this register to configure the USB3 PHY and PIPE
	 * interface.
	 */
	GUSB3PIPECTL0_data *gusb3pipectl0 = gusb3pipectl0_setup();

	/*
	 * Refer Table 1-61
	 * Tx Deemphasis (TxDeemphasis)
	 */
	gusb3pipectl0->SS_TX_DE_EMPHASIS = 0x1;

	if(g_suspend_mode_enable)
	{
		gusb3pipectl0->SUSPENDENABLE = 0x1;
	}

	/*
	 * Delay PHY power change from P0 to P1/P2/P3 when link state
	 * changing from U0 to U1/U2/U3 respectively.
	 */
	gusb3pipectl0->DELAYP1TRANS = 0x1;

	/*
	 * Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until 8B10B error
	 * occurs, or Pipe3_RxValid drops to 0.
	 */
	gusb3pipectl0->DelayP1P2P3 = 0x1;

	/*
	 * When set, the controller always requests PHY power change
	 * from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition.
	 */
	gusb3pipectl0->request_p1p2p3 = 0x1;
	/*
	 * USB3 PHY Soft Reset
	 * After setting this bit to '1', the software needs to clear this bit.
	 */
	gusb3pipectl0->PHYSoftRst = 0x1;

	if(gusb3pipectl0_write()!=0)
	{
		return -2;
	}


	/*
	 * USB 2.0 PHY Internal CSR Configuration
	 */

	U2phy_misc_ctrl2_reset_status_reg *u2phy_misc_ctrl2_reset_status_reg_data
	= u2phy_misc_ctrl2_reset_status_reg_setup();

	u2phy_misc_ctrl2_reset_status_reg_data->USB2_PHY_CLK_SEL = 0x1;
	u2phy_misc_ctrl2_reset_status_reg_data->usb2phy_internal_rst = 0x1;
	u2phy_misc_ctrl2_reset_status_reg_data->usb2phy_refclk_sel = 0x1;

	if(u2phy_misc_ctrl2_reset_status_reg_write() != 0)
	{
		return -3;
	}

	U2phy_misc_ctrl1_reg *u2phy_misc_ctrl1_reg_data
	= u2phy_misc_ctrl1_reg_setup();

	u2phy_misc_ctrl1_reg_data->BIST_EN_N = 0x1;

	if(!g_external_clock_enable)
	{
		u2phy_misc_ctrl1_reg_data->SEL_INTERNALCLK = 0x1;
	}

	if(u2phy_misc_ctrl1_reg_write() != 0)
	{
		return -4;
	}
	/*
	 * USB 3.0 PHY Internal CSR Configuration
	 */

	u3phy_pma_debug_sel_misc_reg *u3phy_pma_debug_sel_misc_reg_data
	= u3phy_pma_debug_sel_misc_reg_setup();
	u3phy_pma_debug_sel_misc_reg_data->usb3phy_internal_rstn = 0x1;
	u3phy_pma_debug_sel_misc_reg_data->usb3phy_refclk_sel = 0x1;

	if(u3phy_pma_debug_sel_misc_reg_write() != 0)
	{
		return -5;
	}

	/*
	 * USB 3.0 PHY External CSR Configuration
	 */

	/**
	 * @todo unknown registers and values to be provided by FPGA team.
	 */

	uint32_t *unknown_reg = reg_setup(0x4032 << 2);
	*unknown_reg = 0x00000040;
	if( ltcusb_raw_write() != 0)
	{
		return -6;
	}

	unknown_reg = reg_setup(0x4023 << 2);
	*unknown_reg = 0x90940001;
	if( ltcusb_raw_write() != 0)
	{
		return -7;
	}

	unknown_reg = reg_setup(0x4024 << 2);
	*unknown_reg = 0x3f7a03d0;
	if( ltcusb_raw_write() != 0)
	{
		return -8;
	}

	unknown_reg = reg_setup(0x4025 << 2);
	*unknown_reg = 0x03d09000;
	if( ltcusb_raw_write() != 0)
	{
		return -9;
	}

	if(g_external_clock_enable)
	{
		unknown_reg = reg_setup(0x4010 << 2);
		*unknown_reg = 0x7FE78032;
		if( ltcusb_raw_write() != 0)
		{
			return -10;
		}
	}
	else
	{
		unknown_reg = reg_setup(0x4010 << 2);
		*unknown_reg = 0x7FE7C032;
		if( ltcusb_raw_write() != 0)
		{
			return -11;
		}
	}


	/*
	 * Table 1-57.
	 * Global USB2 PHY Configuration Register.
	 */
	GUSB2PHYCFG0_data *gusb2phycfg0_data = gusb2phycfg0_setup();

	/*
	 * USB 2.0 Turnaround Time (USBTrdTim).
	 */
	gusb2phycfg0_data->USBTRDTIM = 0x9;
	/*
	 * LS Inter-Packet Time (LSIPD).
	 */
	gusb2phycfg0_data->LSIPD = LSIPD_3_bit_times;

	/*
	 * UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal
	 * to be asserted to reset a UTMI PHY.
	 */
	gusb2phycfg0_data->PHYSOFTRST = 0x0;

	if(gusb2phycfg0_write() != 0)
	{
		return -12;
	}

	/*
	 * Table 1-61
	 * Global USB 3.0 PIPE Control Register
	 * The application uses this register to configure the USB3 PHY and PIPE
	 * interface.
	 */
	GUSB3PIPECTL0_data *gusb3pipectl0_data = gusb3pipectl0_setup();

	/*
	 * Refer Table 1-61
	 * Tx Deemphasis (TxDeemphasis)
	 */
	gusb3pipectl0_data->SS_TX_DE_EMPHASIS = 0x1;

	if(g_suspend_mode_enable)
	{
		gusb3pipectl0_data->SUSPENDENABLE = 0x1;
	}

	/*
	 * Delay PHY power change from P0 to P1/P2/P3 when link state
	 * changing from U0 to U1/U2/U3 respectively.
	 */
	gusb3pipectl0_data->DELAYP1TRANS = 0x1;

	/*
	 * Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until 8B10B error
	 * occurs, or Pipe3_RxValid drops to 0.
	 */
	gusb3pipectl0_data->DelayP1P2P3 = 0x1;

	/*
	 * When set, the controller always requests PHY power change
	 * from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition.
	 */
	gusb3pipectl0_data->request_p1p2p3 = 0x1;
	/*
	 * USB3 PHY Soft Reset
	 * After setting this bit to '1', the software needs to clear this bit.
	 */
	gusb3pipectl0_data->PHYSoftRst = 0x0;

	if(gusb3pipectl0_write()!=0)
	{
		return -13;
	}

	return 0;
}