/**
 * @file	trb_fifo.h
 * @brief	Read and Write TRB Buffer values.
 * @note
 *  * ------------------------------------------------------------------
     Copyright (c) 2023 by Lattice Semiconductor Corporation

     ALL RIGHTS RESERVED

------------------------------------------------------------------

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 */

#ifndef INCLUDE_TRB_BUFFER_H_
#define INCLUDE_TRB_BUFFER_H_

#include "ltcusb.h"
#include "ltcusb_data_types.h"
#include "ltcusb_command.h"
#include "trb_fifo.h"
#include "descriptor.h"
#include "descriptor_fifo.h"

#include <stdint.h>

/**
 * @brief	Structure to hold the TRB Buffer, as per table 3.1 of section
 * 			3.1.2.
 */
typedef struct LtcUSB_TRB_struct
{
	/**@brief	bit 31:0; This field indicates Data buffer pointer to low
	 *			32 bit address.
	 */
	uint32_t BPTRL :32;

	/**@brief bit 31:0; Data buffer pointer to high 32-bit address.
	 */
	uint32_t BPTRH :32;

	/**@brief bit 23:0; Buffer Size */
	uint32_t BUFSIZE		:24;

	/**@brief bit 25:24; Packet Count M1 */
	uint32_t PCM1		:2;

	/**@brief bit 26; SPR/Reserved*/
	uint32_t SPR		:1;

	/**@brief bit 27; Reserved*/
	uint32_t reserved_27		:1;

	/**@brief bit 31:28; TRB Status */
	uint32_t TRBSTS		:4;

	/**@brief bit 0; Hardware Owner of Descriptor */
	uint32_t HWO		:1;

	/**@brief bit 1; Last TRB */
	uint32_t LST		:1;

	/**@brief bit 2; Chain Buffers*/
	uint32_t CHN		:1;

	/**@brief bit 3; Continue on Short Packet*/
	uint32_t CSP		:1;

	/**@brief bit 9:4; TRB Control */
	uint32_t TRBCTL		:6;

	/**@brief bit 10; Interrupt on Short Packet / Interrupt on Missed ISOC*/
	uint32_t ISP		:1;

	/**@brief bit 11; Interrupt on Complete*/
	uint32_t IOC		:1;

	/**@brief bit 13:12; Reserved */
	uint32_t reserved_13_12 :2;

	/**@brief bit 29:14; Stream ID / SOF Number */
	uint32_t SID		:16;

	/**@brief bit 31:30; Reserved */
	uint32_t reserved_31_30		:2;

}LtcUSB_TRB;

/**
 * @brief	Write the TRB data to the TRB Buffer at
 * 			the address specified.
 * @return	0 When successful. Negative on error.
 */
extern int ltcusb_trb_write(LtcUSB_TRB* trb);

/**
 * @brief	TRB Control Setup
 *
 * It sets the control setup TRB, write this TRB into TRB FIFO and execute the
 * start transfer command for endpoint zero.
 *
 * @return	0 When success.
 * @retval	-1 ltcusb_trb_write failed.
 * @retval	-2 DEPSTRTXFER command failed.
 */
extern int TRB_control_setup();

/**
 * @brief	TRB control data to send descriptor.
 *
 * Create a TRB for control data. Copy the descriptor into descriptor FIFO.
 * DEPSTRTXFER command for the end point specified.
 *
 * @param size_descriptor Size of descriptor to be sent.
 * @param size_data_buffer	Size of buffer holding the descriptor.
 * @param descriptor_data	Buffer of descriptor.
 * @return 0 When success.
 * @retval	0 Operation successful.
 * @retval	-1 TRB Write failed.
 * @retval	-2 Descriptor FIFO write failed.
 * @retval	-3 DEPSTRTXFER command failed.
 *
 */
extern int TRB_control_data(uint32_t size_descriptor,
		uint32_t size_data_buffer,
		uint32_t descriptor_data[]);

extern int TRB_control_data2(uint32_t size_descriptor,
		uint32_t size_data_buffer,
		uint32_t descriptor_data[]);

/**
 * @brief	Setup TRB for control status 2 and send DEPSTRTXFER command.
 * @return 0 When success.
 * @retval	-1 TRB write failed.
 * @retval	-2 DEPSTRTXFR command failed.
 */
extern int TRB_control_status2();

/**
 * @brief	Setup TRB for control status 3 ans send DEPSTRTXFER command at
 * 			physical endpoint determined by direction.
 * @param direction IN and OUT
 * @return  0 When success.
 * @retval -1 TRB write failed.
 * @retval -2 DEPSTRTXFR command failed.
 */
extern int TRB_control_status3(uint32_t direction);

#endif /* INCLUDE_TRB_BUFFER_H_ */