/** * @file ltcusb_regs_ops.h * @brief USB controller register operations. * @note * * ------------------------------------------------------------------ Copyright (c) 2023 by Lattice Semiconductor Corporation ALL RIGHTS RESERVED ------------------------------------------------------------------ DISCLAIMER: LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE 'S REQUIREMENTS, OR THAT LICENSEE' S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED. 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IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ */ #ifndef INCLUDE_LTCUSB_REGS_OPS_H_ #define INCLUDE_LTCUSB_REGS_OPS_H_ #include "ltcusb.h" #include /** * @brief Bind the structure to the read write register. * @return Pointer to DCTL data structure. Change to the return structure * will directly change the read write register contents. */ #define dctl_setup() reg_setup(DCTL_OFFSET) /** * @brief Read from DCTL Register */ #define dctl_read() ltcusb_raw_read() /** * @brief Write to DCTL Register */ #define dctl_write() ltcusb_raw_write() /** * @brief Bind the GSBUSCFG0_data structure to the read write register. */ #define gsbuscfg0_setup() reg_setup(GSBUSCFG0_OFFSET) /** * @brief Read from GSBUSCFG0 Register */ #define gsbuscfg0_read() ltcusb_raw_read() /** * @brief Write to GSBUSCFG0 Register */ #define gsbuscfg0_write() ltcusb_raw_write() /** * @brief Bind the GSBUSCFG0_data structure to the read write register. */ #define gsbuscfg1_setup() reg_setup(GSBUSCFG1_OFFSET) /** * @brief Read from GSBUSCFG0 Register */ #define gsbuscfg1_read() ltcusb_raw_read() /** * @brief Write to GSBUSCFG0 Register */ #define gsbuscfg1_write() ltcusb_raw_write() /** * @brief Bind the GTXTHRCFG_data structure to the read write register. */ #define gtxthrcfg_setup() reg_setup(GTXTHRCFG_OFFSET) /** * @brief Read from GTXTHRCFG Register */ #define gtxthrcfg_read() ltcusb_raw_read() /** * @brief Write to GTXTHRCFG Register */ #define gtxthrcfg_write() ltcusb_raw_write() /** * @brief Bind the GRXTHRCFG_data structure to the read write register. */ #define grxthrcfg_setup() reg_setup(GRXTHRCFG_OFFSET) /** * @brief Read from GRXTHRCFG Register */ #define grxthrcfg_read() ltcusb_raw_read() /** * @brief Write to GRXTHRCFG Register */ #define grxthrcfg_write() ltcusb_raw_write() /** * @brief Bind the GSNPSID_data structure to the read write register. */ #define gsnpsid_setup() reg_setup(GSBUSCFG1_OFFSET) /** * @brief Read from GSNPSID Register */ #define gsnpsid_read() ltcusb_raw_read() /** * @brief Write to GSNPSID Register */ #define gsnpsid_write() ltcusb_raw_write() /** * @brief Bind the GUID_data structure to the read write register. */ #define guid_setup() reg_setup(GUID_OFFSET) /** * @brief Read from GUID Register */ #define guid_read() ltcusb_raw_read() /** * @brief Write to GUID Register */ #define guid_write() ltcusb_raw_write() /** * @brief Bind the GUSB2PHYCFG0_data structure to the read write register. */ #define gusb2phycfg0_setup() reg_setup(GUSB2PHYCFG0_OFFSET) /** * @brief Read from GUSB2PHYCFG0 Register */ #define gusb2phycfg0_read() ltcusb_raw_read() /** * @brief Write to GUSB2PHYCFG0 Register */ #define gusb2phycfg0_write() ltcusb_raw_write() /** * @brief Bind the GUSB3PIPECTL0_data structure to the read write register. */ #define gusb3pipectl0_setup() reg_setup(GUSB3PIPECTL0_OFFSET) /** * @brief Read from GUSB3PIPECTL0 Register */ #define gusb3pipectl0_read() ltcusb_raw_read() /** * @brief Write to GUSB3PIPECTL0 Register */ #define gusb3pipectl0_write() ltcusb_raw_write() /** * @brief Bind the GTXFIFOSIZ_data structure to the read write register. */ #define gtxfifosiz_setup(ep) reg_setup(GTXFIFOSIZ_OFFSET + (ep)*0x4) /** * @brief Read from GTXFIFOSIZ Register */ #define gtxfifosiz_read() ltcusb_raw_read() /** * @brief Write to GTXFIFOSIZ Register */ #define gtxfifosiz_write() ltcusb_raw_write() /** * @brief Bind the GRXFIFOSIZ_data structure to the read write register. */ #define grxfifosiz_setup(ep) reg_setup(GRXFIFOSIZ_OFFSET + (ep)*0x4) /** * @brief Read from GRXFIFOSIZ Register */ #define grxfifosiz_read() ltcusb_raw_read() /** * @brief Write to GRXFIFOSIZ Register */ #define grxfifosiz_write() ltcusb_raw_write() /** * @brief Initialize and set the GEVNTADR for desired device. * @param device_number The device number whose event address needs to be set. * @param gevntadr_val The 64 bit address to be set. * @return 0 When success. * @note The value of device_number must be lower than * DWC_USB3_DEVICE_NUM_INT. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntadr_init(uint32_t device_number, uint64_t gevntadr_val); /** * @brief Get the event address for desired device. * @param device_number The device number whose event address is wanted. * @param genvtadr_val The pointer to a 64 bit number to hold the address. * @return 0 When success. * @note The value of device_number must be lower than * DWC_USB3_DEVICE_NUM_INT. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntadr_get(uint32_t device_number, uint64_t *genvtadr_val); /** * @brief Initialize and set the global event size for the device. * @param device_number The device number * @param event_size The event buffer size for device number. * @param event_intr_mask The interrupt mask status for device. * @return 0 When success. * @note The value of device_number must be lower than * DWC_USB3_DEVICE_NUM_INT. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntsiz_init(uint32_t device_number, uint32_t event_size, uint32_t event_intr_mask); /** * @brief Get the global event size for the device. * @param device_number The device number * @param event_size The event buffer size for device number. * @param event_intr_mask The interrupt mask status for device. * @return 0 When success. * @note The value of device_number must be lower than * DWC_USB3_DEVICE_NUM_INT. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntsiz_get(uint32_t device_number, uint32_t *event_size, uint32_t *event_intr_mask); /** * @brief Initialize and set the Global event count and event handler. * @param device_number The device number * @param event_count The number of event count. * @param event_hndlr_busy Event handler busy clear by writing one to it. * @return 0 When success. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntcount_init(uint32_t device_number, uint32_t event_count, uint32_t event_hndlr_busy); /** * @brief Get the Global event count and event handler. * @param device_number The device number * @param event_count The number of event count. * @param event_hndlr_busy Event handler busy clear by writing one to it. * @return 0 When success. * @retval 0 Operation Successful. * @retval -1 The device number is invalid. */ int gevntcount_get(uint32_t device_number, uint32_t *event_count, uint32_t *event_hndlr_busy); /**@brief GCTL register setup. */ #define gctl_setup() reg_setup(GCTL_OFFSET) /**@brief Read from GCTL register.*/ #define gctl_read() ltcusb_raw_read() /**@brief Write to GCTL Register. */ #define gctl_write() ltcusb_raw_write() /**@brief DCFG register setup. */ #define dcfg_setup() reg_setup(DCFG_OFFSET) /**@brief Read from DCFG register.*/ #define dcfg_read() ltcusb_raw_read() /**@brief Write to DCFG Register. */ #define dcfg_write() ltcusb_raw_write() /**@brief DEVTEN register setup. */ #define devten_setup() reg_setup(DEVTEN_OFFSET) /**@brief Read from DEVTEN register.*/ #define devten_read() ltcusb_raw_read() /**@brief Write to DEVTEN Register. */ #define devten_write() ltcusb_raw_write() /**@brief DSTS register setup. */ #define dsts_setup() reg_setup(DSTS_OFSET) /**@brief Read from DSTS register.*/ #define dsts_read() ltcusb_raw_read() /**@brief Write to DSTS Register. */ #define dsts_write() ltcusb_raw_write() /** * @brief Set the Endpoint parameter. * @param endpoint The Number of endpoint. * @param par_number The PAR register number to be set. * @param parameter The parameter to be set at the par. * @return 0 When success, negative when failed. * @retval 0 Operation successful. * @retval -1 Invalid PAR number. * @retval -2 Invalid Endpoint. */ int depcmdpar_set(uint32_t endpoint, uint32_t par_number, uint32_t parameter); /** * @brief Get the Endpoint parameter. * @param endpoint The Number of endpoint. * @param par_number The PAR register number to be set. * @param parameter The parameter to be set at the par. * @return 0 When success, negative when failed. * @retval 0 Operation successful. * @retval -1 Invalid PAR number. * @retval -2 Invalid Endpoint. */ int depcmdpar_get(uint32_t endpoint, uint32_t par_number, uint32_t *parameter); /**@brief DEPCMD Register setup for endpoint provided.*/ #define depcmd_setup(ep) reg_setup(DEPCMD_OFFSET + (0x10 * ep)) /**@brief Read from DEPCMD register*/ #define depcmd_read() ltcusb_raw_read() /**@brief Write to DEPCMD register*/ #define depcmd_write() ltcusb_raw_write() /**@brief DALEPENA Register setup for endpoint provided.*/ #define dalepena_setup(ep) reg_setup(DALEPENA_OFFSET) /**@brief Read from DEPCMD register*/ #define dalepena_read() ltcusb_raw_read() /**@brief Write to DEPCMD register*/ #define dalepena_write() ltcusb_raw_write() /**@brief u2phy_misc_ctrl2_reset_status_reg setup for endpoint provided.*/ #define u2phy_misc_ctrl2_reset_status_reg_setup() \ reg_setup(u2phy_misc_ctrl2_reset_status_reg_OFFSET) /**@brief Read from u2phy_misc_ctrl0_reg register*/ #define u2phy_misc_ctrl2_reset_status_reg_read() ltcusb_raw_read() /**@brief Write to u2phy_misc_ctrl0_reg register*/ #define u2phy_misc_ctrl2_reset_status_reg_write() ltcusb_raw_write() /**@brief u2phy_misc_ctrl1_reg Register setup for endpoint provided.*/ #define u2phy_misc_ctrl1_reg_setup() reg_setup(u2phy_misc_ctrl1_reg_OFFSET) /**@brief Read from u2phy_misc_ctrl0_reg register*/ #define u2phy_misc_ctrl1_reg_read() ltcusb_raw_read() /**@brief Write to u2phy_misc_ctrl0_reg register*/ #define u2phy_misc_ctrl1_reg_write() ltcusb_raw_write() /**@brief u3phy_pma_debug_sel_misc_reg setup for endpoint provided.*/ #define u3phy_pma_debug_sel_misc_reg_setup() \ reg_setup(u3phy_pma_debug_sel_misc_reg_OFFSET) /**@brief Read from u2phy_misc_ctrl0_reg register*/ #define u3phy_pma_debug_sel_misc_reg_read() ltcusb_raw_read() /**@brief Write to u2phy_misc_ctrl0_reg register*/ #define u3phy_pma_debug_sel_misc_reg_write() ltcusb_raw_write() #endif /* INCLUDE_LTCUSB_REGS_OPS_H_ */