/**
 * @file	ltcusb_regs_offsets.h
 * @brief	Offesets for the USB controller registers.
 * @note
 *  * ------------------------------------------------------------------
     Copyright (c) 2023 by Lattice Semiconductor Corporation

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 */

#ifndef INCLUDE_LTCUSB_REGS_OFFSETS_H_
#define INCLUDE_LTCUSB_REGS_OFFSETS_H_

#include "ltcusb.h"

/**
 * @brief	Offset of DCTL Register
 */
#define		DCTL_OFFSET				0xc704

/**
 * @brief	Offset of GSBUSCFG0 register
 */
#define		GSBUSCFG0_OFFSET		0xc100

/**
 * @brief	Offset of GSBUSCFG1 register
 */
#define		GSBUSCFG1_OFFSET		0xc104

/**
 * @brief	Offset of GTXTHRCFG register
 */
#define		GTXTHRCFG_OFFSET		0xc108

/**
 * @brief	Offset of GRXTHRCFG register
 */
#define		GRXTHRCFG_OFFSET		0xc10c

/**
 * @brief	Offset of GSNPSID register
 */
#define		GSNPSID_OFFSET			0xc120

/**
 * @brief	Offset of GUID register
 */
#define		GUID_OFFSET				0xc128

/**
 * @brief	Offset of GUSB2PHYCFG0 register
 */
#define		GUSB2PHYCFG0_OFFSET		0xc200

/**
 * @brief	Offset of GUSB3PIPECTL0 register
 */
#define		GUSB3PIPECTL0_OFFSET	0xc2c0

/**
 * @brief	Offset of GTXFIFOSIZ register
 */
#define		GTXFIFOSIZ_OFFSET		0xc300

/**
 * @brief	Offset of GRXFIFOSIZ register
 */
#define		GRXFIFOSIZ_OFFSET		0xc380

/**
 * @brief	Offset of GEVNTADR register
 */
#define		GEVNTADR_OFFSET			0xc400

/**
 * @brief	Offset of GEVNTSIZ register
 */
#define		GEVNTSIZ_OFFSET			0xc408

/**
 * @brief	Offset of GEVNTCOUNT register
 */
#define		GEVNTCOUNT_OFFSET		0xc40c

/**@brief	Offset of GCTL register*/
#define		GCTL_OFFSET				0xc110

/**@brief	Offset of DCFG register*/
#define		DCFG_OFFSET				0xc700

/**@brief	Offset of DEVTEN register*/
#define		DEVTEN_OFFSET			0xc708

/**@brief	Offset of DSTS register*/
#define		DSTS_OFSET				0xc70c

/**@brief	Offset of DEPCMDPAR0 register*/
#define		DEPCMDPAR0_OFFSET		0xc808

/**@brief	Offset of DEPCMD register*/
#define		DEPCMD_OFFSET			0xc80c

/**@brief	Offset of DALEPENA register.*/
#define		DALEPENA_OFFSET			0xc720

/**@brief	Offset of u2phy_misc_ctrl2_reset_status register.*/
#define 	u2phy_misc_ctrl2_reset_status_reg_OFFSET	0x18008

/**@brief	Offset of u2phy_misc_ctrl1_reg register.*/
#define 	u2phy_misc_ctrl1_reg_OFFSET		0x18004

/**@brief	Offset of u2phy_misc_ctrl2_reset_status register.*/
#define 	u3phy_pma_debug_sel_misc_reg_OFFSET		0x14010

#endif /* INCLUDE_LTCUSB_REGS_OFFSETS_H_ */