/*
 * ------------------------------------------------------------------
     Copyright (c) 2023 by Lattice Semiconductor Corporation

     ALL RIGHTS RESERVED

------------------------------------------------------------------

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------------------------------------------------------------------
 *
 */

#include "Initialization_on_Connect_Done.h"

uint32_t g_connect_speed;

int Initialization_onConnect_Done()
{
	/*
	 * Device Status Register. This register indicates the status of the device
	 * controller with respect to USB-related events.
	 */
	DSTS_data *dsts = dsts_setup();

	if(dsts_read()!=0)
	{
		return -4;
	}

	/*
	 * Indicates the speed at which the DWC_usb3 controller has
	 * come up after speed detection through a chirp sequence.
	 */
	g_connect_speed = dsts->CONNECTSPD;
	g_connect_speed = (g_connect_speed & (0x7));

	if(g_uart_enable)
	{
		if(g_connect_speed == 0)
		{
			printf("H");
		}
		else if(g_connect_speed == 1)
		{
			printf("F");
		}
		else
		{
			printf("SS");
		}

	}

	DEPCFG_Par1 DEPCFG_Par1_EP0 = {0};
	DEPCFG_Par1_EP0.event_enable_mask = 0x5;

	DEPCFG_Par0 DEPCFG_Par0_EP0 = {0};
	DEPCFG_Par0_EP0.config_action = modify_endpoint_state_config_action;
	if(g_connect_speed == super_speed_usb)
	{
		DEPCFG_Par0_EP0.maximum_packet_size = 0x200;
	}
	else
	{
		DEPCFG_Par0_EP0.maximum_packet_size = 0x40;
	}

	if(DEPCFG_cmd(0x0, 0x00000000,&DEPCFG_Par1_EP0,&DEPCFG_Par0_EP0)!=0)
	{
		return -1;
	}

	DEPCFG_Par1 DEPCFG_Par1_EP1 ={0};
	DEPCFG_Par1_EP1.USB_ep_dir = 0x1;
	DEPCFG_Par1_EP1.event_enable_mask = 0x5;

	DEPCFG_Par0 DEPCFG_Par0_EP1 ={0};
	DEPCFG_Par0_EP1.config_action =  modify_endpoint_state_config_action;
	if(g_connect_speed == super_speed_usb)
	{
		DEPCFG_Par0_EP1.maximum_packet_size = 0x200;
	}
	else
	{
		DEPCFG_Par0_EP1.maximum_packet_size = 0x40;
	}

	if(DEPCFG_cmd(0x1, 0x00000000,&DEPCFG_Par1_EP1,&DEPCFG_Par0_EP1) != 0)
	{
		return -2;
	}

	/*
	 * Simulation Speed Up Factor. Program this register (GCTL) to
	 * override scaledown.
	 */
	GCTL_data *gctl = gctl_setup();

	gctl->BYPSSETADDR = 0x0;
	gctl->CORESOFTRESET = 0x0;
	gctl->DEBUGATTACH = 0x0;
	gctl->DISSCRAMBLE = 0x0;
	gctl->DSBLCLKGTNG = 0x0;
	gctl->FRMSCLDWN = 0x0;
	gctl->GblHibernationEn = 0x0;
	gctl->MASTERFILTBYPASS = 0x0;
	gctl->SOFITPSYNC = 0x0;
	gctl->U1U2TimerScale = 0x0;

	/*
	 * Table 1-17, Link waits for 8us of LFPS before it detects a valid
	 * U2 Exit.
	 */
	gctl->U2EXIT_LFPS = 0x1;

	/*
	 * Table 1-17,
	 * Port capability direction for device configuration.
	 */
	gctl->PRTCAPDIR = 0x2;

	/*
	 * Table 1-17
	 * If this bit is set, then device attempts three more times to
	 * connect at SS, even if it previously failed to operate in SS
	 * mode. For each attempt, the device checks receiver
	 * termination eight times.
	 */
	gctl->U2RSTECN = 0x1;

	/*
	 * Table 1-17,
	 * More info from PWERDNSCALE from the document.
	 */
	gctl->PWRDNSCALE = 0x0618;

	if(g_simulation_enable)
	{
		if(g_usb_speed == 0x4)
		{
			/*
			 * RAM Clock Select (RAMClkSel) : pipe clock
			 */
			gctl->RAMCLKSEL = 0x01;
			/*
			 * Table 1-17, Enables scale-down of all timing values except
			 * Device mode suspend and resume. These include Speed
			 * enumeration, HNP/SRP, and Host mode suspend and
			 * resume.
			 */
			gctl->SCALEDOWN = 0x03;//0x02
		}
		else
		{
			/*
			 * Table 1-17, Enables scale-down of all timing values except
			 * Device mode suspend and resume. These include Speed
			 * enumeration, HNP/SRP, and Host mode suspend and
			 * resume.
			 */
			gctl->SCALEDOWN = 0x03;//0x01
		}
	}
	else
	{
		gctl->SCALEDOWN = 0x0;
		/*
		 * RAM Clock Select (RAMClkSel) : pipe clock
		 */
		gctl->RAMCLKSEL = 0x0;
	}

	if(gctl_write()!=0)
	{
		return -3;
	}

	g_bconfiguration_value = 0x00000000;

	g_clear_remote_wakeup = 0;

	/*
	 * Initialize Descriptors
	 */
	if(descriptor_init() != 0)
	{
		return -5;
	}

	return 0;
}