/*
 * trb_buffer.c
 *
 *  Created on: 15-Jun-2023
 *      Author: vivek
 */

#include <stdint.h>
#include "trb_fifo.h"

static inline int is_even(uint32_t value)
{
	return ((value & 0x1))?FALSE:TRUE;
}

int ltcusb_trb_write(LtcUSB_TRB* trb)
{
	uint8_t* data = (uint8_t*)trb;

	uint32_t* data32 = (uint32_t*)data;

	for(int i=0;i<4;i++)
	{
		if(ltcusb_fifo_write(TRB_FIFO_ADDR_RV, data32[i]) != 0)
		{
			return -1;
		}
	}

	return 0;
}

int TRB_control_setup()
{
	LtcUSB_TRB control_setup_trb = {0};

	control_setup_trb.BPTRL = REQ_FIFO_ADDR_USB23;
	control_setup_trb.BUFSIZE = 0x8;

	control_setup_trb.HWO = 1;
	control_setup_trb.LST = 1;
	control_setup_trb.TRBCTL = control_setup_trbctl;
	control_setup_trb.IOC = 1;

	if(ltcusb_trb_write(&control_setup_trb) !=0 )
	{
		return -1;
	}

	DEPSTRTXFER_Par1 Depstrtxfer_par1_data = {0};
	Depstrtxfer_par1_data.TDAddr_Low = TRB_FIFO_ADDR_USB23;

	DEPSTRTXFER_Par0 Depstrtxfer_par0_data = {0};
	Depstrtxfer_par0_data.TDAddr_High = 0;

	if(DEPSTRTXFER_cmd(0, &Depstrtxfer_par1_data, &Depstrtxfer_par0_data) != 0)
	{
		return -2;
	}

	return 0;
}

int TRB_control_data(uint32_t size_descriptor,
		uint32_t size_data_buffer,
		uint32_t descriptor_data[])
{
	LtcUSB_TRB control_data_trb = {0};

	control_data_trb.BPTRL = DESC_FIFO_ADDR_USB23;
	control_data_trb.BUFSIZE = (size_descriptor & 0xFFFFFF);

	control_data_trb.HWO = 1;
	control_data_trb.LST = 1;
	control_data_trb.TRBCTL = control_data_trbctl;
	control_data_trb.IOC = 1;

	if(ltcusb_trb_write(&control_data_trb) !=0 )
	{
		return -1;
	}

	if(descriptor_fifo_write(size_data_buffer, descriptor_data) != 0)
	{
		return -2;
	}

	// This is for control transfer, the IP requires it to be 0x1 at endpoint
	DEPSTRTXFER_Par1 Depstrtxfer_par1_data = {0};
	Depstrtxfer_par1_data.TDAddr_Low = TRB_FIFO_ADDR_USB23;

	DEPSTRTXFER_Par0 Depstrtxfer_par0_data = {0};
	Depstrtxfer_par0_data.TDAddr_High = 0;

	if(DEPSTRTXFER_cmd(0x1, &Depstrtxfer_par1_data, &Depstrtxfer_par0_data) != 0)
	{
		return -3;
	}

	return 0;
}

int TRB_control_data2(uint32_t size_descriptor,
		uint32_t size_data_buffer,
		uint32_t descriptor_data[])
{
	LtcUSB_TRB control_data_trb = {0};

	control_data_trb.BPTRL = DESC_FIFO_ADDR_USB23;
	control_data_trb.BUFSIZE = (size_descriptor & 0xFFFFFF);

	control_data_trb.HWO = 1;
	control_data_trb.LST = 1;
	control_data_trb.TRBCTL = control_data_trbctl;
	control_data_trb.IOC = 1;


	uint32_t rem = size_data_buffer%4;

	if(rem != 0)
	{
		size_data_buffer += (4-rem);
	}

	uint32_t loops = size_data_buffer / 4;

	if(!is_even(loops))
	{
		size_data_buffer += 4;
	}

	size_data_buffer >>= 2;


	if(ltcusb_trb_write(&control_data_trb) !=0 )
	{
		return -1;
	}

	if(descriptor_fifo_write(size_data_buffer, descriptor_data) != 0)
	{
		return -2;
	}

	// This is for control transfer, the IP requires it to be 0x1 at endpoint
	DEPSTRTXFER_Par1 Depstrtxfer_par1_data = {0};
	Depstrtxfer_par1_data.TDAddr_Low = TRB_FIFO_ADDR_USB23;

	DEPSTRTXFER_Par0 Depstrtxfer_par0_data = {0};
	Depstrtxfer_par0_data.TDAddr_High = 0;

	if(DEPSTRTXFER_cmd(0x1, &Depstrtxfer_par1_data, &Depstrtxfer_par0_data) != 0)
	{
		return -3;
	}

	return 0;
}

int TRB_control_status2()
{
	LtcUSB_TRB control_status2_trb = {0};

	control_status2_trb.BPTRL = TRB_FIFO_ADDR_USB23;
	control_status2_trb.BUFSIZE = 0;

	control_status2_trb.HWO = 1;
	control_status2_trb.LST = 1;
	control_status2_trb.TRBCTL = control_status_2_trbctl;
	control_status2_trb.IOC = 1;

	if(ltcusb_trb_write(&control_status2_trb) !=0 )
	{
		return -1;
	}

	DEPSTRTXFER_Par1 Depstrtxfer_par1_data = {0};
	Depstrtxfer_par1_data.TDAddr_Low = TRB_FIFO_ADDR_USB23;

	DEPSTRTXFER_Par0 Depstrtxfer_par0_data = {0};
	Depstrtxfer_par0_data.TDAddr_High = 0;

	if(DEPSTRTXFER_cmd(0x1, &Depstrtxfer_par1_data, &Depstrtxfer_par0_data) != 0)
	{
		return -2;
	}

	return 0;
}

int TRB_control_status3(uint32_t direction)
{
	if(direction != ep_in)
	{
		direction = ep_out;
	}

	LtcUSB_TRB control_status3_trb = {0};

	control_status3_trb.BPTRL = TRB_FIFO_ADDR_USB23;
	control_status3_trb.BUFSIZE = 0;

	control_status3_trb.HWO = 1;
	control_status3_trb.LST = 1;
	control_status3_trb.TRBCTL = control_status_3_trbctl;
	control_status3_trb.IOC = 1;

	if(ltcusb_trb_write(&control_status3_trb) !=0 )
	{
		return -1;
	}

	DEPSTRTXFER_Par1 Depstrtxfer_par1_data = {0};
	Depstrtxfer_par1_data.TDAddr_Low = TRB_FIFO_ADDR_USB23;

	DEPSTRTXFER_Par0 Depstrtxfer_par0_data = {0};
	Depstrtxfer_par0_data.TDAddr_High = 0;

	if(DEPSTRTXFER_cmd(direction, &Depstrtxfer_par1_data, &Depstrtxfer_par0_data) != 0)
	{
		return -2;
	}

	return 0;
}

//int set_physical_endpoints(uint8_t ep_number,
//					EP_dir direction,
//					endpoint_type type,
//					trb_control trbctl_type)
//{
//	LtcUSB_TRB trb_data = {0};
//
//	trb_data.BPTRL = INTERRUPT_ADDRESS_USB23;
//	trb_data.BUFSIZE = INTERRUPT_OUT_HS_DATA_SIZE;
//
//	trb_data.HWO = 1;
//	trb_data.LST = 1;
//	trb_data.TRBCTL = trbctl_type;
//	trb_data.IOC = 1;
//
//	if(ltcusb_trb_write(&trb_data) !=0 )
//	{
//		return -1;
//	}
//
//	return 0;
//}