/*
 * ltcusb_regs.h
 *
 *  Created on: 19-Apr-2023
 *      Author: pushpkant
 */

/**
 * @file	ltcusb_regs.h
 * @brief	Register MAP and their associated structures and methods.
 */

#ifndef INCLUDE_LTCUSB_REGS_H_
#define INCLUDE_LTCUSB_REGS_H_

#include "ltcusb_regs_offsets.h"
#include "ltcusb_regs_ops.h"

#include "ltcusb.h"
#include <stdint.h>

/**
 * @brief	Represents Number of Device Mode Event Buffers
 */
#define		DWC_USB3_DEVICE_NUM_INT		1

/**
 * @brief	Represents number of device mode endpoints.
 */
#define		DWC_USB3_NUM_EPS			32

/**
 * @brief	Holding the data to register DCTL.
 */
typedef struct DCTL_data_struct {
	/**@brief bit 0, reserved.*/
	uint32_t reserved_0 : 	1;
	/**@brief bit 4:1, Test control.*/
	uint32_t TSTCTL 	:	4;
	/**@brief bit 8:5, USB link status change request.*/
	uint32_t ULSTCHNGREQ :	4;
	 /**@brief bit 9, Accept U1 Enable.*/
	uint32_t ACCEPTU1ENA :	1;
	/**@brief bit 10, Initiate U1 Enable.*/
	uint32_t INITU1ENA	:	1;
	/**@brief bit 11, Accept U2 Enable.*/
	uint32_t ACCEPTU2ENA :	1;
	/**@brief bit 12, Initiate U2 Enable.*/
	uint32_t INITU2ENA	:	1;
	/**@brief bit 15:13, reserved.*/
	uint32_t reserved_15_13:3;
	/**@brief bit 16, Controller Save state.*/
	uint32_t CSS		:	1;
	/**@brief bit 17, Controller Restore state.*/
	uint32_t CRS		:	1;
	/**@brief bit 18, L1 Hibernation Enable.*/
	uint32_t L1HibernationEn:1;
	/**@brief bit 19, Keep Connect.*/
	uint32_t KeepConnect :	1;
	/**@brief bit 23:20, LPM NYET Threshold. */
	uint32_t LPM_NYET_thres:4;
	/**@brief bit 28:24, HIRD Threshold (HIRD_Thres).*/
	uint32_t HIRDTHRES	:	5;
	/**@brief bit 29, reserved.*/
	uint32_t reserved_29:	1;
	/**@brief bit 30, Core Soft Reset.*/
	uint32_t CSFTRST	:	1;
	/**@brief bit 31, Run/Stop.*/
	uint32_t RUN_STOP	:	1;
}DCTL_data;

/**
 * @brief	Holding the data to register Global SoC Bus Configuration Register 0
 */
typedef struct GSBUSCFG0_data_struct {
	/** @brief bit 0; Undefined Length INCR Burst Type Enable. */
	uint32_t INCRBRSTENA	:1;

	/** @brief bit 1; INCR4 Burst Type Enable.*/
	uint32_t INCR4BRSTENA	:1;

	/**
	 * @brief bit 2; INCR8 Burst Type Enable.
	 */
	uint32_t INCR8BRSTENA	:1;

	/**
	 * @brief bit 3; INCR16 Burst Type Enable.
	 */
	uint32_t INCR16BRSTENA	:1;

	/**
	 * @brief bit 4; INCR32 Burst Type Enable.
	 */
	uint32_t INCR32BRSTENA	:1;

	/**
	 * @brief bit 5; INCR64 Burst Type Enable.
	 */
	uint32_t INCR64BRSTENA	:1;

	/**
	 * @brief bit 6; INCR128 Burst Type Enable.
	 */
	uint32_t INCR128BRSTENA	:1;

	/**
	 * @brief bit 7; INCR256 Burst Type Enable.
	 */
	uint32_t INCR256BRSTENA	:1;

	/**
	 * @brief bit 9:8; Reserved
	 */
	uint32_t reserved_9_8	:2;

	/**
	 * @brief bit 10; Descriptor Access is Big Endian.
	 */
	uint32_t DESBIGEND		:1;

	/**
	 * @brief bit 11; Data Access is Big Endian.
	 */
	uint32_t DATBIGEND		:1;

	/**
	 * @brief bit 15:12; Reserved.
	 */
	uint32_t reserved_15_12	:4;

	/**
	 * @brief bit 19:16; DESWRREQINFO
	 */
	uint32_t DESWRREQINFO	:4;

	/**
	 * @brief bit 23:20; DATWRREQINFO
	 */
	uint32_t DATWRREQINFO	:4;

	/**
	 * @brief bit 27:24; DESRDREQINFO
	 */
	uint32_t DESRDREQINFO	:4;

	/**
	 * @brief bit 31:28; DATRDREQINFO
	 */
	uint32_t DATRDREQINFO	:4;

}GSBUSCFG0_data;

/**
 * @brief	Global SoC Bus Configuration Register 1.
 */
typedef struct GSBUSCFG1_data_struct {
	/**
	 * @brief bit 7:0; Reserved.
	 */
	uint32_t reserved_7_0	:8;

	/**
	 * @brief bit 11:8;AXI Pipelined Transfers Burst Request Limit.
	 */
	uint32_t PipeTransLimit	:4;

	/**
	 * @brief bit 12; 1k Page Boundary Enable.
	 */
	uint32_t EN1KPAGE		:1;

	/**
	 * @brief bit 31:13; Reserved.
	 */
	uint32_t reserved_31_13	:(31-13+1);

}GSBUSCFG1_data;

/**
 * @brief	Global Tx Threshold Control Register.
 */
typedef struct GTXTHRCFG_data_struct {
	/**
	 * @brief bit 10:0; Reserved for future use.
	 */
	uint32_t reserved_10_0	:11;

	/**
	 * @brief bit 13:11;Reserved (Rsvd/Rs).
	 */
	uint32_t reserved_13_11	:3;

	/**
	 * @brief bit 14; Reserved1(Rsvd/Rs).
	 */
	uint32_t reserved_14		:1;

	/**
	 * @brief bit 15; Reserved_15.
	 */
	uint32_t reserved_15	:1;

	/**
	 * @brief bit 23:16; USB Maximum TX Burst Size.
	 */
	uint32_t UsbMaxTxBurstSize	:8;

	/**
	 * @brief bit 27:24; USB Transmit Packet Count.
	 */
	uint32_t UsbTxPktCnt	:4;

	/**
	 * @brief bit 28; Reserved.
	 */
	uint32_t reserved_28	:1;

	/**
	 * @brief bit 29; USB Transmit Packet Count Enable.
	 */
	uint32_t UsbTxPktCntSel	:1;

	/**
	 * @brief bit 30; Reserved.
	 */
	uint32_t reserved_30	:1;

	/**
	 * @brief bit 31; Reserved.
	 */
	uint32_t reserved_31	:1;

}GTXTHRCFG_data;

/**
 * @brief	Global Rx Threshold Control Register.
 */
typedef struct GRXTHRCFG_data_struct {
	/**
	 * @brief bit 12:0; Space reserved in Rx FIFO for ISOC OUT.
	 */
	uint32_t ResvISOCOUTSpc	:13;

	/**
	 * @brief bit 14:13;Reserved.
	 */
	uint32_t reserved_14_13	:2;

	/**
	 * @brief bit 15; Reserved.
	 */
	uint32_t reserved_15	:1;

	/**
	 * @brief bit 18:16; Reserved.
	 */
	uint32_t reserved_18_16	:3;

	/**
	 * @brief bit 23:19; USB Maximum Receive Burst Size.
	 */
	uint32_t UsbMaxRxBurstSize	:5;

	/**
	 * @brief bit 27:24; USB Receive Packet Count.
	 */
	uint32_t UsbRxPktCnt	:4;

	/**
	 * @brief bit 28; Reserved.
	 */
	uint32_t reserved_28	:1;

	/**
	 * @brief bit 29; USB Receive Packet Count Enable.
	 */
	uint32_t UsbRxPktCntSel	:1;

	/**
	 * @brief bit 31:30; Reserved.
	 */
	uint32_t reserved_31_30	:2;

}GRXTHRCFG_data;

/**
 * @brief Global Synopsys ID Register
 */
typedef struct GSNPSID_data_struct {
	/**
	 * @brief bit 31:0; Holding the synopsis ID.
	 */
	uint32_t SYNOPSYSID;
}GSNPSID_data;

/**
 * @brief Global User ID Register
 */
typedef struct GUID_data_struct {
	/**
	 * @brief bit 31:0; Holding the USERID.
	 */
	uint32_t USERID;
}GUID_data;

/**
 * @brief	Global USB2 PHY Configuration Register
 *
 * The application must program this register before starting any transactions
 * on either the SoC bus or
 * the USB.
 * @note In Device-only configurations, only one register is needed.
 * @note In Host mode, per-port registers are implemented.
 */
typedef struct GUSB2PHYCFG0_data_struct {
	/**@brief bit 2:0; HS/FS Timeout Calibration (TOutCal)*/
	uint32_t TOutCal	:3;
	/**@brief bit 3; PHY Interface (PHYIf)*/
	uint32_t PHYIF		:1;
	/**@brief bit 4; ULPI or UTMI+ Select (ULPI_UTMI_Sel)*/
	uint32_t ULPI_UTMI_Sel	:1;
	/**@brief bit 5; Full-Speed Serial Interface Select (FSIntf)*/
	uint32_t FSINTF			:1;
	/**@brief bit 6; Suspend USB2.0 HS/FS/LS PHY (SusPHY)*/
	uint32_t SUSPENDUSB20	:1;
	/**@brief bit 7; USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
	* Transceiver Select*/
	uint32_t PHYSEL			:1;
	/**@brief bit 8; Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM)
	* The application uses this bit to control utmi_sleep_n and
	* utmi_l1_suspend_n assertion to the PHY in the L1 state.*/
	uint32_t ENBLSLPM		:1;
	/**@brief bit 9;Transceiver Delay*/
	uint32_t XCVRDLY		:1;
	/**@brief bit 13:10; USB 2.0 Turnaround Time (USBTrdTim)*/
	uint32_t USBTRDTIM		:4;
	/**@brief bit 14; reserved.*/
	uint32_t reserved_14	:1;
	/**@brief bit 15; ULPI Auto Resume (ULPIAutoRes)*/
	uint32_t ULPIAUTORES	:1;
	/**@brief bit 16; reserved.*/
	uint32_t reserved_16	:1;
	/**@brief bit 17; ULPI External VBUS Drive (ULPIExtVbusDrv)*/
	uint32_t ULPIEXTVBUSDRV	:1;
	/**@brief bit 18; ULPI External VBUS Indicator (ULPIExtVbusIndicator)
	* Indicates the ULPI PHY VBUS over-current indicator.*/
	uint32_t ULPIEXTVBUSINDIACTOR	:1;
	/**@brief bit 21:19; LS Inter-Packet Time (LSIPD)*/
	uint32_t LSIPD					:3;
	/**@brief bit 24:22; LS Turnaround Time (LSTRDTIM)*/
	uint32_t LSTRD					:3;
	/**@brief bit 25; Overriding the FS/LS disconnect time to 32us.*/
	uint32_t OVRD_FSLS_DISC_TIME	:1;
	/**@brief bit 26; The application driver uses this bit to control the HSIC
	* enable/disable function. When set to '1', this bit overrides and
	* functionally inverts the "if_select_hsic" input signal.*/
	uint32_t INV_SEL_HSIC			:1;
	/**@brief bit 28:27; This bit is used in the HSIC device mode of operation. By
	* default, the connect duration for the HSIC device controller is
	* thrice the strobe period. You can change this duration to 4, 5,
	* or 6 times the strobe period by setting the value of this field to
	* 1, 2, or 3. This value is added to the default connect duration.*/
	uint32_t HSIC_CON_WIDTH_ADJ		:2;
	/**@brief bit 29; Support the LPM over ULPI without NOPID token to the ULPI
	* PHY.*/
	uint32_t ULPI_LPM_WITH_OPMODE_CHK	:1;
	/**@brief bit 30; Specifies whether your USB 2.0 PHY provides a free-running
	* PHY clock, which is active when the clock control input is
	* active.*/
	uint32_t U2_FREECLK_EXISTS			:1;
	/**@brief bit 31; UTMI PHY Soft Reset (PHYSoftRst)*/
	uint32_t PHYSOFTRST					:1;
}GUSB2PHYCFG0_data;

/**
 * @brief	Global USB 3.0 PIPE Control Register
 * The application uses this register to configure the USB3 PHY
 * and PIPE interface.
 * @note Device-only configuration requires only one register.
 * @note In Host mode, registers are implemented for
 * each port.
 * @note GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode.
 */
typedef struct GUSB3PIPECTL0_data_struct {
	/**@brief bit 0; Elastic Buffer Mode (ElasticBufferMode)*/
	uint32_t ELASTIC_BUFFER_MODE	:1;
	/**@brief bit 2:1; Tx Deemphasis (TxDeemphasis)*/
	uint32_t SS_TX_DE_EMPHASIS		:2;
	/**@brief bit 5:3; Tx Margin[2:0] (TxMargin)*/
	uint32_t TX_MARGIN				:3;
	/**@brief bit 6; Tx Swing (TxSwing)*/
	uint32_t TX_SWING				:1;
	/**@brief bit 7; This field is not used.*/
	uint32_t SSICEn					:1;
	/**@brief bit 8; RX_DETECT to Polling.LFPS Control*/
	uint32_t RX_DETECT_to_Polling_LFPS_Control :1;
	/**@brief bit 9; LFPS Filter (LFPSFilt)*/
	uint32_t LFPSFILTER				:1;
	/**@brief bit 10; P3 Exit Signal in P2 (P3ExSigP2)*/
	uint32_t P3ExSigP2				:1;
	/**@brief bit 11; P3 P2 Transitions OK (P3P2TranOK)*/
	uint32_t P3P2TranOK				:1;
	/**@brief bit 12; LFPS P0 Align*/
	uint32_t LFPSP0Algn				:1;
	/**@brief bit 13; Skip Rx Detect*/
	uint32_t SkipRxDet				:1;
	/**@brief bit 14; Abort Rx Detect in U2 (AbortRxDetInU2)*/
	uint32_t AbortRxDetInU2			:1;
	/**@brief bit 16:15; PIPE Data Width (DatWidth)*/
	uint32_t DATWIDTH				:2;
	/**@brief bit 17; Suspend USB3.0 SS PHY (Suspend_en)*/
	uint32_t SUSPENDENABLE			:1;
	/**@brief bit 18; Delay PHY power change from P0 to P1/P2/P3 when link state
	* changing from U0 to U1/U2/U3 respectively.*/
	uint32_t DELAYP1TRANS			:1;
	/**@brief bit 21:19; Delay P1P2P3*/
	uint32_t DelayP1P2P3			:3;
	/**@brief bit 22; Disable Receiver Detection in U3/Rx.Det*/
	uint32_t DisRxDetU3RxDet		:1;
	/**@brief bit 23; Start Receiver Detection in U3/Rx.Detect
	* (StartRxdetU3RxDet)*/
	uint32_t StartRxDetU3RxDet		:1;
	/**@brief bit 24; Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3)*/
	uint32_t request_p1p2p3			:1;
	/**@brief bit 25; U1U2exitfail to Recovery (u1u2exitfail_to_recov)*/
	uint32_t u1u2exitfail_to_recov	:1;
	/**@brief bit 26; Ping Enhancement Enable (ping_enhancement_en)*/
	uint32_t ping_enhancement_en	:1;
	/**@brief bit 27; Ux Exit in Px (Ux_exit_in_Px)*/
	uint32_t Ux_exit_in_Px			:1;
	/**@brief bit 28; Disabled receiver detection in P3 (DisRxDetP3)*/
	uint32_t DisRxDetP3				:1;
	/**@brief bit 29; P3 OK for SSInactive (SSIP3ok)*/
	uint32_t U2P3ok					:1;
	/**@brief bit 30; HstPrtCmpl*/
	uint32_t HstPrtCmpl				:1;
	/**@brief bit 31; USB3 PHY Soft Reset*/
	uint32_t PHYSoftRst				:1;
}GUSB3PIPECTL0_data;

/**
 * @brief	Global Transmit FIFO Size Register for one end point.
 */
typedef struct GTXFIFOSIZ_EP_struct {
	/**@brief bit 15:0; TxFIFO Depth*/
	uint32_t TXFDEP_N		:16;
	/**@brief bit 31:16; Transmit FIFOn RAM Start Address*/
	uint32_t TXFSTADDR_N	:16;
}GTXFIFOSIZ_EP;

/**
 * @brief	Global Transmit FIFO Size Register
 */
typedef struct GTXFIFOSIZ_data_struct {
	/**@brief GTXFIFOSIZ_EP for 32 endpoints.*/
	GTXFIFOSIZ_EP *GTXFIFOSIZ_EP[DWC_USB3_NUM_EPS];
}GTXFIFOSIZ_data;

/**
 * @brief	Global Receive FIFO Size Register for one end point.
 */
typedef struct GRXFIFOSIZ_EP_struct {
	/**@brief bits 15:0; RxFIFO Depth (RxFDep_n)*/
	uint32_t RXFDEP_N		:16;
	/**@brief bits 31:16; RxFIFOn RAM Start Address (RxFStAddr_n)*/
	uint32_t RXFSTADDR_N	:16;
}GRXFIFOSIZ_EP;

/**
 * @brief	Global Receive FIFO Size Register
 */
typedef struct GRXFIFOSIZ_data_struct {
	/**@brief GRXFIFOSIZ_EP for 32 endpoints*/
	GRXFIFOSIZ_EP *GRXFIFOSIZ_EP[DWC_USB3_NUM_EPS];
}GRXFIFOSIZ_data;

/**
 * @brief	Global Event Buffer Address (Low) Register
 */
typedef struct GEVNTADRLO_data_struct {
	/**@brief Event Buffer Address (EvntAdrLo)*/
	uint32_t EVNTADRLO;
}GEVNTADRLO_data;

/**
 * @brief	Global Event Buffer Address (High) Register
 */
typedef struct GEVNTADRHI_data_struct {
	/**@brief Event Buffer Address (EvntAdrHi)*/
	uint32_t EVNTADRHI;
}GEVNTADRHI_data;

/**
 * @brief	Global Event Buffer Address Register
 * This register holds the Event Buffer DMA Address pointer. Software must
 * initialize this address once
 * during power-on initialization. Software must not change the value of this
 * register after it is initialized.
 * Software must only use the GEVNTCOUNTn register for event processing. The
 * lower n bits of the
 * address must be GEVNTSIZn.EVNTSiz-aligned.
 */
typedef struct GEVNTADR_data_dev_struct {
	/**@brief GeventAddr Low register.*/
	GEVNTADRLO_data *LO;
	/**@brief GeventAddr High Register.*/
	GEVNTADRHI_data *HI;
}GEVNTADR_data_dev;

/**
 * @brief	One GEVNTADR_data structure for each device.
 */
typedef struct GEVNTADR_struct {
	/**@brief Array of number of devices. */
	GEVNTADR_data_dev dev[DWC_USB3_DEVICE_NUM_INT];
}GEVNTADR;

/**
 * @brief	Global Event Buffer Size Register.
 * This register holds the Event Buffer Size and the Event Interrupt Mask bit.
 * During power-on initialization, software must initialize the size with the
 * number of bytes allocated for the Event Buffer. The Event Interrupt Mask will
 * mask the interrupt, but events are still queued. After configuration,
 * software must preserve the Event Buffer Size value when changing the Event
 * Interrupt Mask.
 */
typedef struct GEVNTSIZ_dev_data_struct {
	/**@brief bit 15:0; Event Buffer Size in bytes (EVNTSiz).*/
	uint32_t EVENTSIZ		:16;
	/**@brief bit 30:16; Reserved.*/
	uint32_t reserved_30_16	:15;
	/**@brief bit 31; Event Interrupt Mask (EvntIntMask).*/
	uint32_t EVNTINTRPTMASK	:1;
}GEVNTSIZ_dev_data;

/**
 * @brief	Global Event Buffer Size Register array of Event buffer for each
 * 			device.
 */
typedef struct GEVNTSIZ_data_struct {
	/**@brief Array of Event Size buffer for each device. */
	GEVNTSIZ_dev_data *dev[DWC_USB3_DEVICE_NUM_INT];
}GEVNTSIZ_data;

/**
 * @brief	Global Event Buffer Count Register
 * This register holds the number of valid bytes in the Event Buffer. During
 * initialization, software must initialize the count by writing 0 to the Event
 * Count field. Each time the hardware writes a new event to the Event Buffer,
 * it increments this count. Most events are four bytes, but some events may
 * span over multiple four byte entries. Whenever the count is greater than
 * zero and if enabled, conditions for interrupt moderation are satisfied,
 * the hardware raises the corresponding interrupt line (depending on the
 * EvntIntMask bit in the GEVNTSIZn register). On an interrupt, software
 * processes one or more events out of the Event Buffer. Afterwards, software
 * must write the Event Count field with the number of bytes it processed. If
 * Interrupt Moderation is enabled, then software needs to clear
 * EVNT_HAN-DLER_BUSY bit.
 * Clock crossing delays may result in the continuous assertion of the
 * interrupt after software acknowledges the last event. Therefore,
 * when the interrupt line is asserted, software must read the GEVNT-COUNT
 * register and only process events if the GEVNTCOUNT is greater than 0.
 */
typedef struct GEVNTCOUNT_dev_data_struct {
	/**@brief bit 15:0; Event Count (EVNTCount)*/
	uint32_t EVNTCOUNT	:16;
	/**@brief bit 30:16; Reserved*/
	uint32_t reserved_30_16	:15;
	/**@brief bit 31; Event Handler Busy*/
	uint32_t EVNT_HANDLER_BUSY	:1;
}GEVNTCOUNT_dev_data;

/**
 * @brief	Global Event Buffer Count Register for each device.
 *
*/
typedef struct GEVNTCOUNT_data_struct {
	/**@brief gevent count register for each device.*/
	GEVNTCOUNT_dev_data *dev[DWC_USB3_DEVICE_NUM_INT];
}GEVNTCOUNT_data;

/**
 * @brief	Global Core Control Register
 */
typedef struct GCTL_data_struct {
	/**@brief bit 0;Disable Clock Gating (DsblClkGtng)*/
	uint32_t DSBLCLKGTNG	:1;
	/**@brief bit 1; This bit enables hibernation at the global level.*/
	uint32_t GblHibernationEn	:1;
	/**@brief bit 2; This bit is added to improve interoperability with a
	 * third-party host/device controller.
	 */
	uint32_t U2EXIT_LFPS		:1;
	/**@brief bit 3; Disable Scrambling (DisScramble)*/
	uint32_t DISSCRAMBLE		:1;
	/**@brief bit 5:4; Scale-Down Mode (ScaleDown)*/
	uint32_t SCALEDOWN			:2;
	/**@brief bit 7:6; RAM Clock Select (RAMClkSel)*/
	uint32_t RAMCLKSEL			:2;
	/**@brief bit 8; Debug Attach*/
	uint32_t DEBUGATTACH		:1;
	/**@brief bit 9; Disable U1/U2 timer Scaledown (U1U2TimerScale).*/
	uint32_t U1U2TimerScale		:1;
	/**@brief bit 10; If this bit is set to '0' operating in host mode, the
	 * controller keeps the UTMI/ULPI PHY on the first port in a
	 * non-suspended state whenever there is a SuperSpeed port
	 * that is not in Rx.Detect, SS.Disable and U3.
	 * If this bit is set to '1' operating in host mode, the controller
	 * keeps the UTMI/ULPI PHY on the first port in a
	 * non-suspended state whenever the other non-SuperSpeed
	 * ports are not in a suspended state. This feature is useful
	 * because it saves power by suspending UTMI/ULPI when
	 * SuperSpeed only is active, and it helps resolve when the PHY
	 * does not transmit a host resume unless it is placed in suspend
	 * state. This bit must be programmed as a part of initialization at
	 * power-on reset, and must not be dynamically changed.
	 */
	uint32_t SOFITPSYNC			:1;
	/**@brief bit 11; Core Soft Reset (CoreSoftReset)*/
	uint32_t CORESOFTRESET		:1;
	/**@brief bit 13:12; PRTCAPDIR: Port Capability Direction (PrtCapDir)*/
	uint32_t PRTCAPDIR			:2;
	/**@brief bit 15:14; This field scales down device view of a SOF/USOF/ITP
	 * duration.
	 */
	uint32_t FRMSCLDWN			:2;
	/**@brief bit 16; If the SuperSpeed connection fails during POLL or LMP
	 * exchange, the device connects at non-SS mode.
	 */
	uint32_t U2RSTECN			:1;
	/**@brief bit 17; Bypass SetAddress in Device Mode.*/
	uint32_t BYPSSETADDR		:1;
	/**@brief bit 18; Master Filter Bypass*/
	uint32_t MASTERFILTBYPASS	:1;
	/**@brief bit 31:19; Power Down Scale (PwrDnScale)*/
	uint32_t PWRDNSCALE			:(31-19+1);
}GCTL_data;

/**
 * @brief	Device Configuration Register.
 * This register configures the controller in Device mode after power-on or
 * after certain control commands or enumeration.
 * @warning Do not make changes to this
 * register after initial programming.
 */
typedef struct DCFG_data_struct {
	/**@brief bit 2:0; Device Speed.
	 * Indicates the speed at which the application requires the controller to
	 * connect, or the maximum speed the application can support.
	 * However, the actual bus speed is determined only after the chirp
	 * sequence is completed.
	 */
	uint32_t DEVSPD		:3;
	/**@brief bit 9:3; Device Address.
	 * The application must perform the following:
	 * -# Program this field after every SetAddress request.
	 * -# Reset this field to zero after USB reset.
	 */
	uint32_t DEVADDR	:7;
	/**@brief bit 11:10; Reserved */
	uint32_t reserved_11_10	:2;
	/**@brief bit 16:12; Interrupt number
	 * Indicates interrupt/EventQ number on which non-endpoint-specific
	 * device-related interrupts (see DEVT) are generated.
	 */
	uint32_t INTRNUM		:5;
	/**@brief bit 21:17; Number of Receive Buffers.
	 * This bit indicates the number of receive buffers to be reported in the
	 * ACK TP.
	 */
	uint32_t NUMP			:5;
	/**@brief bit 22; LPM Capable
	 * The application uses this bit to control the LPM capabilities of the
	 * DWC_usb3 controller. If the controller operates as a non-LPM-capable
	 * device, it cannot respond to LPM transactions.
	 */
	uint32_t LPMCAP			:1;
	/**@brief bit 23; IgnoreStreamPP This bit only affects stream-capable bulk
	 * endpoints.
	 */
	uint32_t IgnStrmPP		:1;
	/**@brief bit 24; Reserved.*/
	uint32_t StopOnDisconnect	:1;
	/**@brief bit 31:25; Reserved.*/
	uint32_t reserved_31_25		:7;
}DCFG_data;

/**
 * @brief	Device Event Enable Register.
 */
typedef struct DEVTEN_data_struct {
	/**@brief bit 0; Disconnect Detected Event Enable*/
	uint32_t DISSCONNEVTEN	:1;
	/**@brief bit 1; USB Reset Enable*/
	uint32_t USBRSTEVTEN	:1;
	/**@brief bit 2; Connection Done Enable*/
	uint32_t CONNECTDONEEVTEN	:1;
	/**@brief bit 3; USB/Link State Change Event Enable*/
	uint32_t ULSTCNGEN			:1;
	/**@brief bit 4; U3/L2 or U3/L2L1 Resume Detected Event Enable.*/
	uint32_t WKUPEVTEN			:1;
	/**@brief bit 5; This bit enables/disables the generation of the Hibernation
	 * Request Event
	 */
	uint32_t HibernationReqEvtEn	:1;
	/**@brief bit 6; U3/L2 or U3/L2L1 Suspend Event Enable.*/
	uint32_t U3L2L1SuspEn			:1;
	/**@brief bit 7; Start of (u)frame*/
	uint32_t SOFTEVTEN				:1;
	/**@brief bit 8; L1 Suspend Event Enable*/
	uint32_t L1SUSPEN				:1;
	/**@brief bit 9; Erratic Error Event Enable*/
	uint32_t ERRTICERREVTEN			:1;
	/**@brief bit 11:10; reserved.*/
	uint32_t reserved_11_10			:2;
	/**@brief bit 12; Vendor Device Test LMP Received Event
	 * (VndrDevTstRcvedEn)
	 */
	uint32_t VENDEVTSTRCVDEN		:1;
	/**@brief bit 13; reserved.*/
	uint32_t StopOnDisconnectEn		:1;
	/**@brief bit 14; L1 Resume Detected Event Enable.*/
	uint32_t L1WKUPEVTEN			:1;
	/**@brief bit 15; Reserved*/
	uint32_t reserved_15			:1;
	/**@brief bit 16; ECC Error Enable.*/
	uint32_t ECCERREN				:1;
	/**@brief bit 31:17; Reserved*/
	uint32_t reserved_31_17			:15;
}DEVTEN_data;

/**
 * @brief	Device Status Register. This register indicates the status of the device
 * 			controller with respect to USB-related events.
 */
typedef struct DSTS_data_struct {
	/**@brief bit 2:0; Connected Speed (ConnectSpd)
	* Indicates the speed at which the DWC_usb3 controller has
	* come up after speed detection through a chirp sequence.*/
	uint32_t CONNECTSPD	:3;

	/**@brief bit 16:3; Frame/Microframe Number of the Received SOF.*/
	uint32_t SOFFN	:14;

	/**@brief bit 17; RxFIFO Empty.*/
	uint32_t RXFIFOEMPTY	:1;

	/**@brief bit 21:18; USB/Link State. */
	uint32_t USBLNKST			:4;

	/**@brief bit 22; Device Controller Halted.*/
	uint32_t DEVCTRLHLT			:1;

	/**@brief bit 23; Core Idle.
	 */
	uint32_t COREIDLE	:1;

	/**@brief bit 24; SSS Save State Status.*/
	uint32_t SSS			:1;

	/**@brief bit 25; RSS Restore State Status*/
	uint32_t RSS				:1;

	/**@brief bit 27:26; Reserved. */
	uint32_t reserved_27_26				:2;

	/**@brief bit 28; Save Restore Error. Currently not supported.*/
	uint32_t SRE			:1;

	/**@brief bit 29; Device Controller Not Ready.*/
	uint32_t DCNRD			:1;

	/**@brief bit 31:30; Reserved.
	 */
	uint32_t reserved_31_30		:2;

}DSTS_data;

/**
 * @brief	Device Physical Endpoint-n Command Parameter Register
 * 			(DEPCMDPARxn)
 *
 * 			This register indicates the physical endpoint command Parameter.
 * @note 	It must be programmed before issuing the command.
 */
typedef struct DEPCMDPAR_data_reg_struct {
	/**@brief bit 31:0; Parameter*/
	uint32_t PARAMETER		:32;
}DEPCMDPAR_data_reg;

/**
 * @brief	Device Physical Endpoint-n Command Register
 *
 * This register enables software to issue physical endpoint-specific commands.
 * This register contains command, control, and status fields relevant to the
 * current generic command, while the DEPCM-DPAR[2:0]n registers provide
 * command parameters and return status information. Several fields (including
 * Command Type) are write-only, so their read values are undefined. After
 * power-on, prior to issuing the first endpoint command, the read value of
 * this register is undefined. In particular, the CmdAct bit may be set after
 * power-on. In this case, it is safe to issue an endpoint command.
 */
typedef struct DEPCMD_data_struct {
	/**@brief bit 3:0; Command Type */
	uint32_t CMDTYP	:4;
	/**@brief bit 7:4; Reserved*/
	uint32_t reserved_7_4	:4;
	/**@brief bit 8; Command Interrupt on Complete (CmdIOC)*/
	uint32_t CMDIOC			:1;
	/**@brief bit 9; Reserved*/
	uint32_t reserved_9		:1;
	/**@brief bit 10; Command Active (CmdAct)*/
	uint32_t CMDACT			:1;
	/**@brief bit 11; HighPriority/ForceRM (HiPri_ForceRM)*/
	uint32_t HIPRI_FORCERM	:1;
	/**@brief bit 15:12; Command Completion Status (CmdStatus)*/
	uint32_t CMDSTATUS		:4;
	/**@brief bit 31:16; Command Parameters or Event Parameters*/
	uint32_t COMMANDPARAM	:16;
}DEPCMD_data;

#define	DEPCMD_BIT_3_0_CMDTYPE_MASK 	(0xF)
#define	DEPCMD_BIT_10_CMDACT			(10)
#define	DEPCMD_BIT_8_CMDIOC				(8)
#define	DEPCMD_BIT_11_HIPRI_FORCERM		(11)

/**
 * @brief	Device Active USB Endpoint Enable Register.
 *
 * This register indicates whether a USB endpoint is active in a given
 * configuration or interface.
 */
typedef struct DALEPENA_data_struct {
	/**@brief bit 31:0; This field indicates if a USB endpoint is active in
	 * the current configuration and interface. It applies to USB IN endpoints
	 * 0.15 and OUT endpoints 0.15, with one bit for each of the 32 possible
	 * endpoints. Even numbers are for USB OUT endpoints, and odd numbers are
	 * for USB IN endpoints.
	 */
	uint32_t USBACTEP;
}DALEPENA_data;

/**
 * @brief	u2phy_misc_ctrl2_reset_status_reg.
 */
typedef struct U2phy_misc_ctrl2_reset_status_reg_data_struct {
	/**@brief bit 0;  XCLK12MOUTEN*/
	uint32_t XCLK12MOUTEN	:1;
	/**@brief bit 3:1; TEST_LOOP*/
	uint32_t TEST_LOOP		:3;
	/**@brief bit 4; RX_LP_EN*/
	uint32_t RX_LP_EN		:1;
	/**@brief bit 7:5; REG20_ADJ*/
	uint32_t REG20_ADJ		:3;
	/**@brief bit 8; USB2_PHY_CLK_SEL*/
	uint32_t USB2_PHY_CLK_SEL	:1;
	/**@brief bit 9; usb2phy_internal_rst*/
	uint32_t usb2phy_internal_rst	:1;
	/**@brief bit 10; usb2phy_refclk_sel*/
	uint32_t usb2phy_refclk_sel		:1;
	/**@brief bit 11; BIST_DONE_U2PHY*/
	uint32_t BIST_DONE_U2PHY	:1;
	/**@brief bit 12; BIST_ERR_U2PHY*/
	uint32_t BIST_ERR_U2PHY	:1;
	/**@brief bit 31:13; Reserved*/
	uint32_t reserved_31_13		:19;

}U2phy_misc_ctrl2_reset_status_reg;

/**
 * @brief	u2phy_misc_ctrl1_reg.
 */
typedef struct U2phy_misc_ctrl1_reg_data_struct {
	/**@brief bit 0;  CALIB_ONCE_EN*/
	uint32_t CALIB_ONCE_EN	:1;
	/**@brief bit 2:1; HS_EMP_ADJ*/
	uint32_t HS_EMP_ADJ		:2;
	/**@brief bit 4:3; SQL_CUR_ADJ*/
	uint32_t SQL_CUR_ADJ	:2;
	/**@brief bit 7:5; PLLBW_SEL*/
	uint32_t PLLBW_SEL		:3;
	/**@brief bit 8; BIST_EN_N*/
	uint32_t BIST_EN_N		:1;
	/**@brief bit 9; SCP_EN*/
	uint32_t SCP_EN			:1;
	/**@brief bit 10; SEL_12_24M*/
	uint32_t SEL_12_24M		:1;
	/**@brief bit 11; HS_LP_MODE_EN*/
	uint32_t HS_LP_MODE_EN	:1;
	/**@brief bit 15:12; SQL_VTH_ADJ*/
	uint32_t SQL_VTH_ADJ	:4;
	/**@brief bit 16; HS_EMP_EN*/
	uint32_t HS_EMP_EN		:1;
	/**@brief bit 17; RSTN_BYPASS*/
	uint32_t RSTN_BYPASS	:1;
	/**@brief bit 19:18; CDR_BW_SEL*/
	uint32_t CDR_BW_SEL		:2;
	/**@brief bit 23:20; CDR_TIMING_SEL*/
	uint32_t CDR_TIMING_SEL	:4;
	/**@brief bit 24; SEL_INTERNALCLK*/
	uint32_t SEL_INTERNALCLK	:1;
	/**@brief bit 27:25; XOSC_CUR_ADJ*/
	uint32_t XOSC_CUR_ADJ	:3;
	/**@brief bit 31:28; DISC_ADJ*/
	uint32_t DISC_ADJ		:4;

}U2phy_misc_ctrl1_reg;

/**
 * @brief	u3phy_pma_debug_sel_misc register
 */
typedef struct u3phy_pma_debug_sel_misc_reg_data_struct {
	/**@brief bit 7:0;  PMA_DEBUG_SEL0*/
	uint32_t PMA_DEBUG_SEL0	:8;
	/**@brief bit 15:8; PMA_DEBUG_SEL1*/
	uint32_t PMA_DEBUG_SEL1	:8;
	/**@brief bit 16; USB3_PHY_CLK_SEL*/
	uint32_t USB3_PHY_CLK_SEL	:1;
	/**@brief bit 17; usb3phy_internal_rstn*/
	uint32_t usb3phy_internal_rstn	:1;
	/**@brief bit 18; usb3phy_refclk_sel*/
	uint32_t usb3phy_refclk_sel	:1;
	/**@brief bit 19; BIST_DONE_U3PHY*/
	uint32_t BIST_DONE_U3PHY	:1;
	/**@brief bit 20; BIST_FAIL_U3PHY*/
	uint32_t BIST_FAIL_U3PHY		:1;
	/**@brief bit 31:21; Reserved*/
	uint32_t reserved_31_21	:11;

}u3phy_pma_debug_sel_misc_reg;

#endif /* INCLUDE_LTCUSB_REGS_H_ */